Datacenter Compute SoC Architect

MediaTek Research Lab Inc.; San Jose (CA); On-site; USD 211,000 - 356,000; Full time

Benefits offered by this job

Health insurance

Life insurance

Disability insurance

401K

Paid holidays

Sick leave

Vacation time

Parental leave

Job summary

MediaTek seeks a visionary Datacenter Compute SoC Architect to define scalable datacenter processors, balancing power, performance, and area while meeting cloud workloads. You will collaborate with CPU core architects, IP teams, and software engineers to deliver world‑class silicon for data center AI infrastructure.

Open to San Jose, San Diego, Portland, and Austin locations, with leadership across RTL, verification, and silicon bring‑up phases to ensure robust, scalable solutions for cloud

Qualifications

• Education: Bachelor's or Master's in Electrical/Electrical/Computer Engineering or Computer Science.
• 10+ years in SoC/Compute/architecture with 3+ years in datacenter or server SoCs.
• Deep understanding of CPU architectures (ARM/x86/RISC‑V).
• Extensive knowledge of coherent fabrics and interconnects (CHI/AXI/NoC).
• Strong memory hierarchy understanding (DDR4/5, LPDDR, HBM).
• Solid grasp of high-speed I/O (PCIe, CXL, Ethernet).
• Excellent written and verbal communication for cross‑functional teams.

Responsibilities

• Lead architectural definition of next‑gen datacenter Compute SoCs.
• Define requirements and drive IP selections (PCIe Gen5/6, CXL, DDR5/HBM, NoC).
• Perform PPA trade‑offs to meet datacenter efficiency targets.
• Collaborate on multi‑die/chiplet packaging and interconnects (UCIe).
• Partner with firmware, OS, and cloud software teams for HW/SW co‑design.
• Develop use cases with performance modeling teams and guide SystemC models.
• Provide technical leadership through RTL implementation, verification, and silicon bring‑up.

Skills

CPU architectures

SoC architecture

Coherent interconnects

Memory hierarchy

High-speed I/O

Technical leadership

Cross-functional collaboration

Education

Bachelor’s or Master’s in EE/CE/CS

Tools

NoC design

SystemC modeling

C++ modeling

Job description

MediaTek’s Data Center team is at the forefront of innovation, driving the development of cutting-edge technologies that power the world's most advanced data centers. We are a dynamic group of system architects, packaging technology developers, and SoC design experts dedicated to creating high-performance, efficient, and reliable solutions. Our team collaborates closely to push the boundaries of technology, ensuring optimal performance, power efficiency, and scalability for data center applications. Join our Data Center team and be a part of the technological revolution that is shaping the future of data centers. If you are passionate about innovation and have the expertise to drive strategic technology development, we would love to hear from you. We are seeking a highly experienced and visionary Datacenter Compute SoC Architect to lead the definition, design, and optimization of our next-generation high-performance computing SoCs. In this critical role, you will be responsible for defining the system-on-chip architecture for scalable datacenter processors, balancing Power, Performance, and Area (PPA) constraints while meeting aggressive cloud-scale workloads. You will work cross-functionally with CPU/Compute core architects, IP designers, performance modeling teams, and software/firmware engineers to deliver world-class silicon that powers the future of cloud computing and AI infrastructure. Location: open to San Jose, San Diego, Portland and Austin.

Main Requirements and Qualifications

• Qualifications
• Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Experience: 10+ years of proven industry experience in SoC, Compute/CPU, or system architecture, with a minimum of 3 years focusing on high-performance server, datacenter, or network processor SoCs.
• Deep understanding of high-performance CPU architectures (ARM, x86, or RISC-V) or Compute architectures.
• Extensive knowledge of coherent fabrics and interconnects (e.g., ARM AMBA CHI, AXI, proprietary NoCs).
• Strong expertise in memory hierarchy, cache coherency protocols, and main memory technologies (DDR4/5, LPDDR, HBM).
• Solid understanding of high-speed I/O interfaces (PCIe, CXL, Ethernet).
• Communication: Exceptional written and verbal communication skills, with the ability to distill complex architectural concepts into clear specifications for cross-functional teams.
• Salary range: $211,000- $356,000
• Employee may be eligible for performance bonus, short and long term incentive programs. Actual total compensation will be dependent upon the individual's skills, experience and qualifications. In addition, MediaTek provides a variety of benefits including comprehensive health insurance coverage, life and disability insurance, savings plan, Company paid holidays, Sick Leave, Vacation time, Parental leave, 401K and more.
• MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation.

Key Responsibilities

• SoC Architecture Definition: Lead the architectural definition of next-generation datacenter Compute SoCs, including core/instance counts, cache hierarchies, coherent interconnects, and memory subsystems.
• IP Selection & Integration: Define requirements and drive decisions for third- party and internal IPs (e.g., PCIe Gen 5/6, CXL, DDR5/HBM controllers, Network-on-Chip/NoC, and security enclaves).
• PPA Optimization: Conduct rigorous Power, Performance, and Area (PPA) trade-off analysis to ensure the SoC meets strict datacenter efficiency and performance-per-watt targets.
• Advanced Packaging Strategy: Collaborate with packaging teams on multi-die/chiplet-based architectures, die-to-die (D2D) interconnect protocols (e.g., UCIe), and advanced thermal solutions.
• HW/SW Co-Design: Partner closely with firmware, OS, and cloud infrastructure software teams to ensure the hardware architecture optimally supports modern hypervisors, cloud-native workloads, and virtualization technologies.
• Performance Modeling: Work with the performance modeling team to define use cases, guide the creation of C++/SystemC architectural models, and analyze simulation data to identify bottlenecks.
• Technical Leadership: Write detailed architecture specifications and serve as the technical lead during the RTL implementation, verification, and silicon bring-up phases.