Principal SoC Integration Flow Architect - Automation

MediaTek Research Lab Inc.; San Jose (CA); On-site; USD 211,000 - 286,000; Full time

Benefits offered by this job

Comprehensive health insurance

Paid time off (PTO)

401K plan

Job summary

MediaTek Research Lab Inc. is searching for a Principal SoC Integration Flow Architect specializing in automation. This role is pivotal in leading the architectural design for a new Top-level Integration Flow framework, using tools like Python or C++ to ensure seamless IP integration.

The ideal candidate will have over 8 years of experience in SoC Integration and RTL Design, along with expertise in scripting languages. The position offers a comprehensive salary range between $211,000 and $286,000, with additional benefits including health insurance and performance bonuses.

Qualifications

• Proven experience in SoC Integration and RTL Design.
• Expertise in scripting and software engineering applied to EDA flows.
• Familiarity with automated SoC compilers.

Responsibilities

• Design and implement a scalable SoC assembly framework.
• Define and leverage metadata standards for seamless IP integration.
• Build advanced capabilities for automated RTL generation.

Skills

SoC Integration

RTL Design (Verilog/SystemVerilog)

Scripting (Python/Perl/Tcl)

EDA Tools

Job description

Principal SoC Integration Flow Architect - Automation

Category

Chip Design

Location

San Jose, CA

Experience

More than 8 Years Work Expe.

Job Description

We are seeking a high-caliber Engineer to lead the architectural design and development of a next-generation Top-level Integration Flow. Your mission is to build a highly automated framework - comparable to SoC Compiler that streamlines the path from IP handoff to full-chip netlist generation.

Key Responsibilities

• Framework Architecture: Design and implement a scalable SoC assembly framework using Python, Perl, Tcl or C++ to automate connectivity, memory map generation, and clock/reset structures.
• Metadata Standardization: Define and leverage metadata standards (e.g., IP-XACT) to enable seamless IP integration and configuration.
• Tool Development: Build advanced "SoC Compiler" capabilities, including automated RTL generation, stitch-rule checking (LINT/CDC), and synthesis-ready top-level packaging.
• Optimization: Collaborate with Front-End and Physical Design teams to integrate PPA-driven constraints into the automation pipeline.
• Location: San Jose, or San Diego, CA

Main Requirements and Qualifications

• Proven experience in SoC Integration and RTL Design (Verilog/SystemVerilog).
• Expertise in scripting and software engineering (Python/Perl/Tcl) applied to EDA flows.
• Familiarity with industry-standard integration tools and the internal logic of automated SoC compilers.
• Salary range: $211,000 - $286,000
• Employee may be eligible for performance bonus, short and long term incentive programs. Actual total compensation will be dependent upon the individual's skills, experience and qualifications. In addition, MediaTek provides a variety of benefits including comprehensive health insurance coverage, life and disability insurance, savings plan, Company paid holidays, Paid time off (PTO), Parental leave, 401K and more.
• MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation.