Compute Subsystem Architect

MediaTek Research Lab Inc.; San Jose (CA); On-site; USD 211,000 - 356,000; Full time

Benefits offered by this job

Comprehensive health insurance coverage

401(k) plan

Paid vacation and holidays

Job summary

MediaTek Research Lab Inc. is seeking a Compute Subsystem Architect to work on advanced Arm computing platform products. The role involves architecting compute subsystems and collaborating with teams on interface definitions.

The ideal candidate has extensive expertise in Arm CMN architecture, a Master's degree in a relevant field, and a minimum of 10 years' experience. The position offers a competitive salary and comprehensive benefits.

Qualifications

• Deep expertise in Arm CMN-series coherent mesh networks.
• Proficiency in AMBA CHI protocol and its mechanisms.
• Experience in architecting for many-core scaling (32+ cores).
• Familiarity with CXL Type-1/2/3 and RAS architecture.
• Minimum 10 years of relevant industry experience.

Responsibilities

• Architect compute subsystems for next-generation ASIC products.
• Build CPU subsystem performance models for AI workloads.
• Drive technology readiness and lead technical engagement with Arm.
• Prepare architecture specifications and present trade-offs.

Skills

Arm CMN-series coherent mesh networks

AMBA CHI protocol

Architecting for many-core scaling

CXL Type-1/2/3

Excellent communication skills

Education

MS in Electrical Engineering, Computer Engineering, or Computer Science

Job description

MediaTek is seeking a Compute Subsystem Architect to define and build capability in this space ahead of product commitment. The role covers the full Neoverse Compute Subsystem scope: core configuration, CMN topology and parameterization, cache/SLC architecture, and CHI coherency behavior. The role also provides architectural guidance on chiplet and 3D‑IC partitioning trade‑offs, collaborating with dedicated packaging and interconnect teams on interface definitions.

Responsibilities

• Architect compute subsystems (CPU cluster, L2/L3/SLC cache, coherent mesh fabric) for next‑generation ASIC and advanced Arm computing platform products.
• Own CMN topology recommendations: mesh dimension, HN‑F/SN‑F/RN‑F placement, SLC distribution, snoop filter policy, and QoS parameters.
• Build CPU subsystem performance models to quantify many‑core scaling: latency, bandwidth‑per‑core, and mesh congestion under AI‑era workload traffic patterns.
• Drive technology readiness: track Arm Neoverse CSS/CMN roadmap, identify IP gaps, and lead technical engagement with Arm on architecture and multi‑die scope.
• Evaluate architectural implications of 3D‑IC and chiplet splits on CMN topology, CHI credit return, and snoop timing; hand off quantified constraints to packaging and physical teams; co‑design while maintaining focus on computing architecture.
• Align design with potential product landing vehicles including custom ASIC solutions and advanced Arm platforms (including future CPU Dielet configurations).
• Prepare architecture specifications and technical documents; present trade‑offs to engineering leadership and executives.

Qualifications

• Deep expertise in Arm CMN‑series coherent mesh networks: topology sizing, HN/SN/RN placement, SLC optimization, QoS. Arm Neoverse CSS experience strongly preferred (required).
• Proficiency in AMBA CHI protocol: transaction types, snoop behavior, credit flow, and debug mechanisms (required).
• Experience architecting for many‑core scaling (32+ cores): coherency overhead, cache/fabric co‑optimization, tail‑latency analysis (required).
• Familiarity with CXL Type‑1/2/3 and server‑class RAS architecture (desired).
• Excellent communication skills; ability to produce high‑quality architecture documents and present complex trade‑offs to both engineers and executives.
• Educational background: MS in Electrical Engineering, Computer Engineering, Computer Science.
• Minimum 10 years of relevant industry experience.
• Architecture definition and technology readiness for Neoverse CSS‑based compute subsystems: CPU cluster, CMN, cache/SLC, and CHI coherency.
• Architectural interface ownership for chiplet/3D‑IC configurations; packaging and D2D implementation handled by dedicated functional teams.
• Opportunity to shape MediaTek’s advanced computing platform strategy and data center CPU roadmap from the ground up.

Compensation & Benefits

• Salary range: $211,000–$356,000.
• Employee may be eligible for performance bonus, short and long term incentive programs. Actual total compensation will be dependent upon the individual’s skills, experience and qualifications.
• MediaTek provides a variety of benefits including comprehensive health insurance coverage, life and disability insurance, savings plan, company paid holidays, sick leave, vacation time, parental leave, 401(k) and more.

MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation.