Next-Gen Core RTL Power, Clocking & Reset Engineer

AMD; Fort Collins (CO); On-site; USD 120,000 - 150,000; Full time

Job summary

AMD is seeking an experienced RTL design engineer to own power management, clocking, and reset RTL for Core Complex designs within the Core Complex Cache Hierarchy team. You will collaborate across Architecture, Physical Design, Verification, and Design-for-Test groups to deliver high-performance RTL and drive next-generation cores with aggressive schedules.

The candidate should have a strong background in Digital RTL Design, Verilog HDL, and scripting, and be capable of mentoring engineers

Qualifications

• Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, or Computer Science.
• Strong analytical thinking and problem-solving skills; ability to guide and develop people.
• Experience delivering high-performance CPU product architecture and implementation with clocks, power, reset, and CCX interactions.

Responsibilities

• Collaborate with Architecture, Physical Design, Verification, and Design-for-Test to design, document, verify, and deliver high-performance Power, Clocking, Reset, and Control Fabric RTL.
• Work across global IP and SoC teams to solve complex architectural interactions and drive product execution.
• Improve CPU design quality, performance, power, and area through innovation and cross-functional collaboration.
• Present solutions to peers and management and mentor engineers across the organization.
• Guide, mentor, and develop engineers across the organization.

Skills

Digital RTL Design

Verilog HDL

Scripting

Education

Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, or Computer Science

Tools

Verilog HDL

Job description

AMD is seeking an experienced RTL design engineer to own power management, clocking, and reset RTL for Core Complex designs within the Core Complex Cache Hierarchy team. You will collaborate across Architecture, Physical Design, Verification, and Design-for-Test groups to deliver high-performance RTL and drive next-generation cores with aggressive schedules.

The candidate should have a strong background in Digital RTL Design, Verilog HDL, and scripting, and be capable of mentoring engineers