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Xcelerium is seeking a New Grad ASIC RTL Design Engineer to contribute to the design of advanced ASIC technology for Physical AI Compute. This on-site full-time position is open to recent graduates in Electrical Engineering or Computer Engineering.
The role involves collaboration with expert chip designers, covering the full hardware development lifecycle from artifacts to RTL design and performance analysis. Strong fundamentals in digital logic, RTL development in Verilog or SystemVerilog, and enthusiasm for complex systems are essential.
Join a pioneering team at Xcelerium as we advance the field of real-time AI computing.
Xcelerium is seeking a New Grad ASIC RTL Design Engineer to contribute to the design of advanced ASIC technology for Physical AI Compute. This on-site full-time position is open to recent graduates in Electrical Engineering or Computer Engineering.
The role involves collaboration with expert chip designers, covering the full hardware development lifecycle from artifacts to RTL design and performance analysis. Strong fundamentals in digital logic, RTL development in Verilog or SystemVerilog, and enthusiasm for complex systems are essential.
Join a pioneering team at Xcelerium as we advance the field of real-time AI computing.