Modeling Architect — Optical AI Inference Accelerator

Neurophos, Inc.; Sunnyvale, Northern (TX, KY); Hybrid; USD 150,000 - 230,000; Full time

Benefits offered by this job

Health coverage

HSA contributions

Unlimited PTO

401(k) + stock options

Voluntary benefits

Personalized benefits

Job summary

Neurophos, Inc. seeks a modeling architect to perform hands-on architecture modeling of the T100 optical inference accelerator, with hardware/software co-design in the loop.

You’ll work with senior engineers on analytical performance models and hardware models, spanning RTL simulation and C++/Python implementations. Expect to own tests, configurations, and plots, and to collaborate with compiler, runtime, and RTL teams.

Qualifications

• BS or MS in Computer Engineering, Electrical Engineering, Computer Science, or a related field.
• 3+ years of experience in hardware modeling, performance simulation, computer architecture, or related work.
• Proficiency in Python or modern C++ (C++17 or later). Python-first and C++-first backgrounds are both welcome.
• Working knowledge of computer architecture and microarchitecture, including pipelines, caches, memory hierarchies, and instruction set architecture (ISA).
• Ability to turn an LLM, GEMM, or accelerator paper into a workload config using Hugging Face or PyTorch.
• Strong debugging skills and the habit of writing down what was run, what was assumed, and what the number means.

Responsibilities

• Bring up inference workloads as they ship, including dense and MoE transformers, hybrid/SSM models, prefill vs decode, KV cache, expert routing, and quantization, plus retrieval, speech, vision, and recommendation workloads where they map onto the accelerator.
• Bind Hugging Face and PyTorch workloads to the programming model and run them on the functional model.
• Co‑design tiling, scheduling, the ISA, the SRAM and High Bandwidth Memory (HBM) hierarchy, and multi‑chip mapping.
• Build in one or more layers of the modeling stack: roofline and limiter studies; Python energy and latency models; C++ functional models of optical GEMM, SRAM vector processors, dataflow engines, and HBM; cycle‑approximate performance and power models; and RTL simulation with Verilator and SystemVerilog.
• Own the tests, configs, and plots behind a result so anyone can rerun it and see what was assumed.
• Use coding agents on real multi-file edits, and own the review of the C++ and SystemVerilog they generate.
• Share results with the architects setting the design, as well as the compiler, runtime, and RTL teams, and carry their questions back into the model stack.

Skills

Python

C++17+

Hardware modeling

Performance simulation

Computer architecture

Hugging Face / PyTorch

Education

BS or MS in Computer Engineering, Electrical Engineering, CS

MS or PhD preferred

Tools

SystemVerilog

Verilator

Verilog

gem5

SystemC

SST

CUDA

PyTorch

Job description

Neurophos, Inc. seeks a modeling architect to perform hands-on architecture modeling of the T100 optical inference accelerator, with hardware/software co-design in the loop.

You’ll work with senior engineers on analytical performance models and hardware models, spanning RTL simulation and C++/Python implementations. Expect to own tests, configurations, and plots, and to collaborate with compiler, runtime, and RTL teams.