Staff Modeling Architect: AI Hardware Co-Design

Neurophos; San Mateo (CA); On-site; USD 150,000 - 210,000; Full time

Benefits offered by this job

Health plan coverage

Unlimited PTO

401(k) matching

Stock options

Voluntary benefits

Job summary

Neurophos is seeking a staff-level modeling architect to translate production models into performance and energy numbers, and to build functional models for booting software before tape-out. You will own workloads, guide tile strategies, and collaborate with RTL, compiler, and runtime teams across hardware/software co-design.

The role emphasizes developing C++/Python models, ensuring consistency across roofline, limiter analyses, and RTL simulations, with mentorship responsibilities for junior

Qualifications

• 8+ years of experience in hardware modeling, functional modeling, performance modeling or accelerator performance analysis.
• Track record of shipping a model or study relied upon by another team (architecture, compiler, customer, or silicon).
• Strong grounding in computer architecture, memory systems, and AI accelerators.
• Experience with discrete-event, cycle-approximate, or cycle-accurate simulators (SystemC, gem5, SST).
• Proficiency in C++ and Python for modeling and analysis.

Responsibilities

• Bring up inference workloads as they ship, including transformers and related workloads.
• Bind Hugging Face and PyTorch workloads to the programming model and runtime.
• Co-design tiling, ISA, memory hierarchy, and multi-chip mapping across pipelines and parallelism.
• Run roofline analyses and design space exploration across microarchitecture options.
• Develop Python energy and latency models covering SRAM/HBM traffic and optical GEMM.

Skills

Hardware modeling

Performance modeling

Python scripting

Mentoring

Communication

Education

BS/MS/PhD in Computer Engineering/Electrical Engineering/Computer Science

Tools

SystemC

gem5

SST

Verilator

SystemVerilog

Job description

Neurophos is seeking a staff-level modeling architect to translate production models into performance and energy numbers, and to build functional models for booting software before tape-out. You will own workloads, guide tile strategies, and collaborate with RTL, compiler, and runtime teams across hardware/software co-design.

The role emphasizes developing C++/Python models, ensuring consistency across roofline, limiter analyses, and RTL simulations, with mentorship responsibilities for junior