Staff Modeling Architect — AI Hardware Co-Design Leader

Neurophos, Inc.; Sunnyvale, Northern (TX, KY); Hybrid; USD 180,000 - 240,000; Full time

Benefits offered by this job

Health plan premiums covered

Unlimited PTO

401(k) matching

Stock options

Voluntary benefits

Job summary

Neurophos, Inc. invites applications for a staff-level modeling architect to bridge production models with performance and energy targets across the T100 architecture.

You’ll bind workloads to the programming model, run them on the model stack, and guide tiling, ISA, memory hierarchy and multi-chip mapping decisions with RTL and compiler teams. You’ll develop Python energy/latency models and C++ functional models, contribute to the simulation kernel, and ensure consistency across roofline,

Qualifications

• BS, MS, or PhD in Computer Engineering, Electrical Engineering, Computer Science, or equivalent practical experience.
• 8+ years of experience in hardware modeling, functional modeling, performance modeling, performance simulation, or accelerator performance analysis.
• Track record of shipping a model or study that another team depended on.
• Judgment to pick the right method for roofline, limiter analysis, analytical models, or RTL simulation.
• Strong grounding in computer architecture, microarchitecture, memory systems, and AI accelerators.
• Modern C++ (C++17 or later) for functional models and simulation infrastructure.
• Python for models, analysis, and plots (NumPy/Pandas/Matplotlib).
• Experience inside discrete-event or cycle-approximate simulators.

Responsibilities

• Bind workloads to programming models and runtimes; develop functional models for software bring-up before tape-out.
• Co-design tiling, ISA, memory hierarchy, NoC, and multi-chip mapping across pipeline and parallelism.
• Develop Python energy and latency models; create optical GEMM and vector-unit models.
• Implement cycle-approximate performance, power and area models; align with RTL.
• Maintain interface specs and collaborate with RTL, compiler, and runtime teams.
• Mentor engineers and define modeling methodology for workload areas.
• Contribute to C++ event-driven simulation kernel and corpus of traces.

Skills

Hardware modeling

Performance modeling

Python

C++

SystemVerilog

RTL

Discrete-event simulation

LLM/accelerator workloads

Education

BS/MS/PhD in Computer Engineering/Electrical Engineering/CS

Tools

SystemC

gem5

SST

Verilator

ONNX/MLIR

Job description

Neurophos, Inc. invites applications for a staff-level modeling architect to bridge production models with performance and energy targets across the T100 architecture.

You’ll bind workloads to the programming model, run them on the model stack, and guide tiling, ISA, memory hierarchy and multi-chip mapping decisions with RTL and compiler teams. You’ll develop Python energy/latency models and C++ functional models, contribute to the simulation kernel, and ensure consistency across roofline,