Modeling Architect for Optical AI Hardware

Neurophos; Austin, Sunnyvale (TX, CA); On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

Health coverage and premiums paid

Unlimited PTO

401(k) matching and stock options

Voluntary benefits

Personalized Benefits

Job summary

Neurophos in Austin/Sunnyvale seeks a modeling architect to work on hands-on architecture modeling for the T100 optical inference accelerator. You will collaborate with senior engineers across analytical and hardware model tracks, shaping how the models reflect real workloads and constraints.

You will build layer upon layer of models in Python and C++, simulate RTL with Verilator, and tie the results to architecture design decisions. This is onsite with strong emphasis on co-design.

Qualifications

• BS or MS in Computer Engineering, Electrical Engineering, Computer Science, or a related field.
• 3+ years of experience in hardware modeling, performance simulation, computer architecture, or related work.
• Proficiency in Python or modern C++ (C++17 or later). Python-first and C++-first backgrounds are both welcome.
• Working knowledge of computer architecture and microarchitecture, including pipelines, caches, memory hierarchies, and ISA.
• Ability to turn an LLM, GEMM, or accelerator paper into a workload config using Hugging Face or PyTorch.
• Strong debugging skills and the habit of writing down what was run, what was assumed, and what the number means.

Responsibilities

• Bring up inference workloads as they ship, including dense and MoE transformers, hybrid/SSM models, prefill vs. decode, KV cache, expert routing, and quantization, plus retrieval, speech, vision, and recommendation workloads where they map onto the accelerator.
• Bind Hugging Face and PyTorch workloads to the programming model and run them on the functional model.
• Co-design tiling, scheduling, the ISA, the SRAM and HBM hierarchy, and multi-chip mapping.
• Build in one or more layers of the modeling stack: roofline and limiter studies; Python energy and latency models; C++ functional models of optical GEMM, SRAM vector processors, dataflow engines, and HBM; cycle-approximate performance and power models; and RTL simulation with Verilator and SystemVerilog.
• Own the tests, configs, and plots behind a result so anyone can rerun it and see what was assumed.
• Use coding agents on real multi-file edits, and own the review of the C++ and SystemVerilog they generate.
• Share results with the architects setting the design, as well as the compiler, runtime, and RTL teams, and carry their questions back into the model stack.

Skills

Python

C++17+

Hardware modeling

Performance simulation

Computer architecture

ISA knowledge

Debugging

Education

BS or MS in Computer Engineering/Electrical Engineering/CS

Tools

Verilator

SystemVerilog

Hugging Face

PyTorch

RTL/SystemC

Job description

Neurophos in Austin/Sunnyvale seeks a modeling architect to work on hands-on architecture modeling for the T100 optical inference accelerator. You will collaborate with senior engineers across analytical and hardware model tracks, shaping how the models reflect real workloads and constraints.

You will build layer upon layer of models in Python and C++, simulate RTL with Verilator, and tie the results to architecture design decisions. This is onsite with strong emphasis on co-design.