Principal MSDV Lead for Power ICs

Allegro MicroSystems; Nebraska; On-site; USD 140,000 - 200,000; Full time

Job summary

Allegro MicroSystems is seeking a Principal Mixed-Signal Design Verification Engineer & Team Lead to drive end-to-end verification for Power ICs. You will lead a skilled team, define state‑of‑the‑art verification methods, and own the full verification cycle from planning to tape-out readiness.

You will collaborate with design and systems teams, architect reusable SystemVerilog/UVM testbenches, and advance AI-driven automation to streamline verification across the global organization.

Qualifications

• 8+ years of hands-on MSDV experience with power-related topologies.
• BS or MS in Electrical Engineering or related field.
• Proven track record of full-chip verification plans and tape-out sign-off.
• Expertise in SystemVerilog, SVA, and UVM methodologies.
• Proficient in scripting (Python, Bash, Perl) for automation.
• Familiarity with Cadence mixed-signal simulation environments.
• Ability to coach and develop junior-to-mid engineers.

Responsibilities

• Lead and mentor the Mixed Signal Verification Team.
• Define and implement advanced mixed-signal verification methodologies, including AI-driven automation.
• Own all aspects of MSDV for complex mixed-signal ICs from test planning to tape-out sign-off.
• Collaborate with Systems and Design Engineering on top-down chip architecture.
• Build robust SystemVerilog/UVM testbenches and reusable class objects.
• Ensure requirements traceability and safety compliance; automate regression flows with GitLab.

Skills

Mixed-Signal Verification

SystemVerilog/UVM

Python scripting

Cadence tools

Leadership/mentoring

Automation tooling (AI)

Education

Electrical Engineering degree

Tools

GitLab

Cadence

Job description

Allegro MicroSystems is seeking a Principal Mixed-Signal Design Verification Engineer & Team Lead to drive end-to-end verification for Power ICs. You will lead a skilled team, define state‑of‑the‑art verification methods, and own the full verification cycle from planning to tape-out readiness.

You will collaborate with design and systems teams, architect reusable SystemVerilog/UVM testbenches, and advance AI-driven automation to streamline verification across the global organization.