Principal Mixed-Signal Verification Leader

Allegro MicroSystems, LLC; Richardson (TX); On-site; USD 140,000 - 210,000; Full time

Job summary

Allegro MicroSystems is seeking a Principal Mixed-Signal Design Verification (MSDV) Engineer & Team Lead to drive the verification of next-gen Power ICs, including motor drivers and PMICs. You will lead a verification team from planning to tape-out sign-off.

The role requires 8+ years in MSDV, expertise in SystemVerilog/UVM/SVA, and strong background in power topologies. You will collaborate with design and systems teams, build scalable testbenches, and advance automation in a global

Qualifications

• 8+ years hands-on MSDV experience.
• Strong background in power topologies (Motor Drivers, PMICs, Gate Drivers).
• Proven track record in full-chip verification planning and tape-out sign-off.
• Expertise in SystemVerilog, SVA, and UVM.
• Scripting in Python, Bash, or Perl for automation.
• Familiarity with Cadence mixed-signal simulation environments.
• Coaching and developing junior-to-mid level engineers.

Responsibilities

• Lead, develop, and mentor the MSDV team.
• Define and implement state-of-the-art MSDV methodologies, including AI-driven automation.
• Own all aspects of design verification for complex mixed-signal ICs from test planning to tape-out.
• Partner with Systems and Design Engineering teams on architecture and feasibility studies.
• Construct reusable SystemVerilog/UVM testbenches and class objects for global use.
• Translate system requirements into automated tests; ensure ISO 26262 or ASIL compliance where applicable.
• Train engineers to interpret analog schematics and generate behavioral models.
• Establish automated regression flows and track pre-silicon issues via GitLab.

Skills

MSDV experience

SystemVerilog

SVA

UVM

Python scripting

Cadence tools

Power IC verification

leadership

Education

Electrical Engineering degree

Tools

Cadence Mixed-Signal

Job description

Allegro MicroSystems is seeking a Principal Mixed-Signal Design Verification (MSDV) Engineer & Team Lead to drive the verification of next-gen Power ICs, including motor drivers and PMICs. You will lead a verification team from planning to tape-out sign-off.

The role requires 8+ years in MSDV, expertise in SystemVerilog/UVM/SVA, and strong background in power topologies. You will collaborate with design and systems teams, build scalable testbenches, and advance automation in a global