Mixed-Signal IP Design Engineer — Silicon Bring-Up

Broadcom Inc.; Chandler (AZ); On-site; USD 110,000 - 176,000; Full time

Benefits offered by this job

Medical, dental and vision plans

401(K) participation including company

Employee Stock Purchase Program (ESPP)

Employee Assistance Program (EAP)

Company paid holidays

Paid sick leave and vacation time

Paid Family Leave and other leaves of

absence

Job summary

Broadcom Inc. in Chandler, AZ is seeking an experienced Mixed-Signal Analog Design Engineer to join our Central Engineering Group. In this role, you will design on-die PVT monitoring IP across leading process nodes.

You will lead circuit design and verification, supervise layouts, build Verilog models, and deliver datasheets and integration documents while supporting post‑silicon bring-up and validation.

Qualifications

• MS or PhD in Electrical Engineering.
• 6+ years of mixed-signal and analog design experience.
• Experience delivering IP and writing datasheets or integration documents.

Responsibilities

• Design schematic architectures for analog and mixed-signal blocks.
• Supervise layout design and verify post-layout using SPICE.
• Build behavioral and gate-level models and verify with Verilog simulations.
• Create datasheets and technical integration documents.
• Oversee post-silicon bring-up and data-driven validation.

Skills

Mixed-signal design

Analog design

Verilog modeling

Circuit verification

Teamwork

Communication

Education

MS or PhD in Electrical Engineering

Tools

Cadence Virtuoso

Spectre

HSPICE

PrimeSim

Synopsys PrimeTime

Xcelium

VCS

Job description

Broadcom Inc. in Chandler, AZ is seeking an experienced Mixed-Signal Analog Design Engineer to join our Central Engineering Group. In this role, you will design on-die PVT monitoring IP across leading process nodes.

You will lead circuit design and verification, supervise layouts, build Verilog models, and deliver datasheets and integration documents while supporting post‑silicon bring-up and validation.