Analog and Mixed Signal Design Engineer

Broadcom Inc.; Chandler (AZ); On-site; USD 110,000 - 176,000; Full time

Benefits offered by this job

Medical, dental and vision plans

401(K) participation including company

Employee Stock Purchase Program (ESPP)

Employee Assistance Program (EAP)

Company paid holidays

Paid sick leave and vacation time

Paid Family Leave and other leaves of

absence

Job summary

Broadcom Inc. in Chandler, AZ is seeking an experienced Mixed-Signal Analog Design Engineer to join our Central Engineering Group. In this role, you will design on-die PVT monitoring IP across leading process nodes.

You will lead circuit design and verification, supervise layouts, build Verilog models, and deliver datasheets and integration documents while supporting post‑silicon bring-up and validation.

Qualifications

• MS or PhD in Electrical Engineering.
• 6+ years of mixed-signal and analog design experience.
• Experience delivering IP and writing datasheets or integration documents.

Responsibilities

• Design schematic architectures for analog and mixed-signal blocks.
• Supervise layout design and verify post-layout using SPICE.
• Build behavioral and gate-level models and verify with Verilog simulations.
• Create datasheets and technical integration documents.
• Oversee post-silicon bring-up and data-driven validation.

Skills

Mixed-signal design

Analog design

Verilog modeling

Circuit verification

Teamwork

Communication

Education

MS or PhD in Electrical Engineering

Tools

Cadence Virtuoso

Spectre

HSPICE

PrimeSim

Synopsys PrimeTime

Xcelium

VCS

Job description

Job Description

Role Overview

Broadcom’s Central Engineering Group is seeking an experienced Mixed-Signal Analog Design Engineer to join our world‑class team. In this position, you will design advanced on‑die Process, Voltage, and Temperature (PVT) monitoring IP. You will work across a wide range of cutting‑edge technologies, including the industry's most advanced process nodes and applications.

Responsibilities

• Circuit Design & Verification: Design schematic architectures for analog and mixed‑signal blocks, including bandgaps, ADCs, DACs, voltage regulators, comparators, and GPIOs.
• Layout & Post‑Layout Validation: Supervise layout design and verify post‑layout design using SPICE simulations to ensure silicon success.
• Digital Modeling: Build behavioral and gate‑level models for IPs and validate functionality through Verilog simulations.
• IP Delivery & Documentation: Create standard EDA tool views (including timing models), and author comprehensive datasheets and technical integration documents.
• Silicon Bring‑up & Validation: Establish post‑silicon testing guidelines and oversee the validation process by analyzing and reviewing test data.

Education & Experience

• MS or PhD in Electrical Engineering.
• 6+ years of mixed‑signal and analog design experience.

Design Expertise

• Deep knowledge of core analog concepts including gain, bandwidth, stability, device physics, circuit reliability, process variation, and the statistical analysis of Monte Carlo simulation results.
• Strong understanding of layout effects on circuit performance.
• Familiarity with Verilog modeling, digital circuits, and standard digital implementation flows.

EDA Tools Proficiency

• Proficiency with Cadence Virtuoso and simulation platforms like Spectre, HSPICE, or PrimeSim.
• Experience with Synopsys PrimeTime and Verilog simulators such as Xcelium or VCS.

Professional Attributes

• Excellent communication and teamwork skills.
• Proven ability to independently navigate complex, new, or unfamiliar engineering challenges.

Desired Skills

• Prior experience building and delivering mixed‑signal IPs.
• General familiarity with laboratory testing methodologies and common bench equipment to effectively guide lab teams.
• Proficiency in scripting languages (Python, Perl, SKILL) to automate design and verification tasks.
• Familiarity with ESD (Electrostatic Discharge) and latch‑up design rules.
• Silicon Failure Analysis (FA) and debugging skills.

Compensation and Benefits

The annual base salary range for this position is USD 109,700.00 To USD 175,500.00. As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Benefits

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

• Medical, dental and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Company paid holidays
• Paid sick leave and vacation time
• Paid Family Leave and other leaves of absence

Equal Opportunity

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

Additional Notes

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Welcome! Thank you for your interest in Broadcom! We are a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions. For more information please visit our video library and check out our Connected by Broadcom series. Follow us on Linked In Broadcom Inc.