I/O Design Engineer — Analog/Mixed-Signal for AI Chips

Broadcom Inc.; Chandler (AZ); On-site; USD 110,000 - 176,000; Full time

Benefits offered by this job

Medical, dental and vision plans

401(K) with company matching

Employee Stock Purchase Program

Job summary

Broadcom Inc. in Chandler, AZ, seeks an I/O Design Engineer with expertise in analog and mixed-signal IC design to contribute to the design and verification of IP and I/Os, including AI-related programs on advanced nodes.

The role involves designing CMOS I/O, bandgap references, op-amps and power-on-reset circuits, running AC/DC simulations, and collaborating with layout teams for physical design and silicon bring-up in test chips and customer products.

Qualifications

• MS or PhD in Electrical Engineering required.
• 6+ years of I/O or analog circuit design experience.
• Proficiency in Cadence Virtuoso schematic/layout and SPICE/Spectre simulations.
• Solid grounding in I/O protocols (GPIO, I2C, I3C, eMMC, RGMII, SPMI).
• Experience with FinFET/GAA nodes and PPA tradeoffs.

Responsibilities

• Design CMOS I/O, bandgap references, op-amps, comparators and POR circuits.
• Run simulations to validate AC/DC performance, signal integrity, jitter and power.
• Perform transistor reliability and EMIR analysis.
• Work with layout teams for physical design and verification.
• Create and maintain Verilog, Synopsys Liberty and IBIS models.
• Develop documentation including datasheets, app notes and integration guides.
• Support chip integration and silicon bring-up in test chips and customer products.

Skills

I/O design

Analog circuit design

Circuit simulation

Verilog modeling

IBIS models

Education

MS or PhD in Electrical Engineering

Tools

Cadence Virtuoso

SPICE/Spectre

Verilog

Synopsys Liberty

IBIS models

Job description

Broadcom Inc. in Chandler, AZ, seeks an I/O Design Engineer with expertise in analog and mixed-signal IC design to contribute to the design and verification of IP and I/Os, including AI-related programs on advanced nodes.

The role involves designing CMOS I/O, bandgap references, op-amps and power-on-reset circuits, running AC/DC simulations, and collaborating with layout teams for physical design and silicon bring-up in test chips and customer products.