Memory Verification Engineer - Pre-Silicon UVM Specialist

Solidigm; California; Hybrid; USD 121,000 - 194,000; Full time

Benefits offered by this job

RSU program

RCU program

Cash bonus

Medical, dental, vision coverage

401(k) company match

Job summary

Solidigm is seeking a senior pre-silicon verification engineer to lead UVM-based verification for advanced 3D NAND designs in a hybrid Rancho Cordova, CA role. You will create test plans, develop directed and constrained-random tests, and drive functional coverage closures with SystemVerilog assertions and mixed-signal modeling.

You will also maintain verification environments, automate workflows, and collaborate across design teams to ensure robust verification results.

Qualifications

• Master’s or higher in Electrical/Computer Engineering, Computer Engineering, or Computer Science.
• 5+ years of relevant pre-silicon verification experience.
• Hands-on with UVM, SystemVerilog Assertions, and formal verification.
• Experience in mixed-signal verification and analog/digital modeling.
• Strong debugging, data analysis, and scripting skills (Python/Perl/Shell).

Responsibilities

• Create and maintain verification test plans based on design specifications.
• Develop UVM-based directed and constrained-random tests, debug simulation failures, and identify issues.
• Define functional coverage models and perform coverage analysis and closure.
• Create and maintain SystemVerilog Assertions (SVA) for 3D NAND designs.
• Develop, maintain, and enhance the UVM verification environment.
• Develop scripts and tools to automate verification workflows, regression execution, results processing, and data collection.

Skills

UVM-based verification

SystemVerilog

Assertions

mixed-signal modeling

debugging

scripting

Education

Master’s degree in Electrical/Computer Engineering or Computer Science

Bachelor’s degree in Electrical/Computer Engineering or Computer Science

Tools

UVM

SystemVerilog

Formal verification

Mixed-signal tools

Simulation tools

Job description

Solidigm is seeking a senior pre-silicon verification engineer to lead UVM-based verification for advanced 3D NAND designs in a hybrid Rancho Cordova, CA role. You will create test plans, develop directed and constrained-random tests, and drive functional coverage closures with SystemVerilog assertions and mixed-signal modeling.

You will also maintain verification environments, automate workflows, and collaborate across design teams to ensure robust verification results.