Memory PHY RTL design Engineer

Mindlance; Boxborough (MA); Hybrid; USD 90,000 - 140,000; Full time

Job summary

Join a forward-thinking company as a Design Engineer, where you'll be at the forefront of developing high-speed Memory PHYs and interface IPs. This role involves collaborating with cross-functional teams to design and implement cutting-edge digital architectures. Your expertise in RTL design and debugging will be crucial as you tackle complex challenges and contribute to innovative solutions. With a focus on teamwork and communication, you'll work alongside talented engineers across various sites. This is an exciting opportunity to make a significant impact in the memory technology sector while advancing your career in a dynamic environment.

Benefits

Health insurance

401(k)

Qualifications

• Experience in digital design engineering and RTL coding.
• Strong analytical and problem-solving skills.

Responsibilities

• RTL design for memory I/O and digital architecture development.
• Collaborate with architects and engineers to verify new features.

Skills

Digital Design Engineering

RTL Design

Debugging Firmware

Verilog

SystemVerilog

C/C++ Programming

Scripting Languages (Python, Perl, TCL)

Understanding of Clocking Architectures

Education

Bachelor's degree in Computer Engineering

Master's degree in Electrical Engineering

Tools

Simulation Tools

UVM Testbenches

Linux

Windows

Job description

Boxborough, MA (Hybrid - 3 days a week)

THE ROLE:

The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware development of high-speed LPDDR, DDR IPs. Be a part of the definition, design, and development phase of industry-leading Memory PHYs and interface IP. This opportunity includes creating new IO designs as well as working on multiple designs and enhancing methodologies in parallel. Join a team that delivers industry-leading IP and collaborate with RTL, FW, circuit, and architecture teams to develop leading-edge and differentiating IPs.

THE PERSON:

You are passionate about modern, complex processor architecture, digital design, and verification. You are a team player with excellent communication skills and experience working with engineers across different sites and time zones. You possess strong analytical and problem-solving skills and are eager to learn and tackle new challenges.

KEY RESPONSIBILITIES:

1. RTL design for memory I/O
2. Develop PHY digital architecture from concept to physical implementation
3. Design, implement, and verify PHY link layer with Analog and System architects
4. Co-design analog and digital components
5. Perform digital design and RTL coding
6. Conduct timing synthesis and drive physical implementation
7. Collaborate with architects, hardware, and firmware engineers to understand and verify new features
8. Build unit tests
9. Debug design failures, identify root causes, and work with DV and firmware teams to resolve issues

PREFERRED EXPERIENCE:

• Experience in digital design engineering
• Proficiency in debugging firmware and RTL code using simulation tools
• Experience with UVM testbenches and working in Linux and Windows environments
• Proficiency in Verilog, SystemVerilog, C, and C++
• Knowledge of scripting languages such as Python, Perl, and TCL is a plus
• Understanding of clocking architectures, synchronization, and CDC methodology
• Experience with SERDES, DDR, Memory Controller, or MAC design is preferred
• Strong understanding of computer organization and architecture
• Mixed signal RTL experience is a plus

ACADEMIC CREDENTIALS:

Bachelor's or Master's degree in Computer Engineering or Electrical Engineering

Job Posting Start Date: 2025-05-26

Job Posting End Date: 2026-05-24

Company Code: United States

Benefits:

• Health insurance
• 401(k)