Memory PHY RTL Design Engineer

TPI Global Solutions; Boxborough (MA); On-site; USD 80,000 - 120,000; Full time

Job summary

An innovative firm is looking for a skilled Memory PHY RTL Design Engineer to contribute to cutting-edge memory interface technologies. In this role, you will design and develop RTL for high-speed memory PHY IP, collaborate on PHY architecture, and work with cross-functional teams to ensure successful verification and validation. You'll leverage your expertise in RTL design and memory interfaces to tackle complex design issues, making a significant impact in the semiconductor industry. If you're passionate about engineering and eager to push the boundaries of technology, this opportunity is perfect for you.

Qualifications

• Experience in RTL design and memory interface technologies.
• Strong understanding of digital design and verification methodologies.

Responsibilities

• Design and develop RTL for high-speed memory PHY IP.
• Collaborate on PHY architecture and digital design implementation.
• Debug and resolve design issues at RTL and firmware levels.

Skills

RTL design experience with Verilog/SystemVerilog

Knowledge of DDR/LPDDR memory interfaces

UVM verification methodology

PHY-level design considerations

Synthesis and timing closure

Scripting skills (Python, Perl, or TCL)

Education

Bachelor's degree in Electrical Engineering

Master's degree in Computer Engineering

Job description

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Senior Recruitment Specialist at TPI Global Solutions

We are seeking a skilled Memory PHY RTL Design Engineer to join our team working on advanced memory interface technologies.

Key Responsibilities:

• Design and develop RTL for high-speed memory PHY IP
• Collaborate on PHY architecture and digital design implementation
• Perform timing synthesis and clock domain crossing analysis
• Work with cross-functional teams on verification and validation
• Debug and resolve design issues at RTL and firmware levels

Required Skills:

• Strong RTL design experience with Verilog/SystemVerilog
• Knowledge of DDR/LPDDR memory interfaces
• Experience with UVM verification methodology
• Understanding of PHY-level design considerations
• Familiarity with synthesis and timing closure

Preferred Qualifications:

• Experience with memory controller designs
• Scripting skills (Python, Perl, or TCL)
• Knowledge of mixed-signal design concepts

Education:

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field

Seniority level

• Mid-Senior level

Employment type

• Contract

Job function

• Engineering, Information Technology, and Design

Industries

• Semiconductor Manufacturing, Computers and Electronics Manufacturing, Electrical Equipment Manufacturing