Memory PHY RTL design Engineer

US Tech Solutions; Boxborough (MA); On-site; USD 80,000 - 120,000; Full time

Job summary

Join a forward-thinking company as a Design Engineer to work on cutting-edge Memory PHYs and interface IPs. This role offers the chance to engage in RTL and firmware development, enhancing methodologies while collaborating with experts across various domains. Ideal candidates will have a strong foundation in digital design, verification, and a passion for complex architectures. If you thrive in a dynamic environment and are eager to tackle challenging problems, this opportunity is perfect for you. Be part of a team that is shaping the future of memory technology!

Qualifications

• Passion for modern processor architecture and digital design.
• Strong analytical and problem-solving skills with a team-oriented approach.

Responsibilities

• RTL design for memory I/O and PHY Digital Architecture development.
• Collaborate with architects and engineers to verify new features.

Skills

Digital design engineering

Debugging firmware and RTL code

UVM testbenches

Verilog

System Verilog

C

C++

Python

Perl

TCL

Clocking architectures

Mixed signal RTL

Education

Bachelor's degree in Computer Engineering

Master's degree in Electrical Engineering

Tools

Simulation tools

Linux

Windows

Job description

• The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware development of high-speed LPDDR, DDR IPs.
• Be a part of the definition, design and development phase of industry-leading Memory PHYs and interface IP.
• This opportunity includes creation of new IO designs as well as working on multiple designs and enhancing methodologies in parallel.
• Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge and differentiating IPs.

The Person:

• You have a passion for modern, complex processor architecture, digital design, and verification in general.
• You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones.
• You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

Key Responsibilities:

• RTL design for memory I/O
• PHY Digital Architecture development from pathfinding, coding, verification to physical implementation
• PHY link layer design, implementation & verification with Analog and System architect.
• PHY Analog/Digital co-design
• Digital design and RTL coding
• Timing Synthesis & Drive Physical implementation
• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
• Build the unit tests
• Debug design failures to determine the root cause; work with DV and firmware engineers to resolve design defects and correct any test issues

Preferred Experience:

• Digital design engineering experience
• Proficient in debugging firmware and RTL code using simulation tools
• Proficient in using UVM testbenches and working in Linux and Windows environments
• Experienced with Verilog, System Verilog, C, and C++
• Excellent knowledge of Verilog, System Verilog and a scripting language; experience with Python, Perl and TCL is a plus
• Knowledge of clocking architectures, synchronization, and CDC methodology
• SERDES, DDR, Memory Controller, or MAC Design experience is preferred
• Strong understanding of computer organization/architecture.
• Mixed signal RTL experience is a plus

Academic Credentials:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

About US Tech Solutions:
US Tech Solutions is a global staff augmentation firm providing a wide range of talent on-demand and total workforce solutions. To know more about US Tech Solutions, please visit www.ustechsolutions.com.

"US Tech Solutions is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran."