Memory PHY RTL Design Engineer

Cynet Systems Inc; Boxborough (MA); On-site; USD 80,000 - 100,000; Full time

Job summary

An innovative firm is seeking a skilled digital design engineer to join their team. In this role, you will design RTL for memory I/O, develop PHY Digital Architecture, and collaborate closely with architects and engineers to verify new features. Your expertise in Verilog, SystemVerilog, and debugging will be crucial in ensuring high-quality designs. This position offers an exciting opportunity to work on cutting-edge technology in a dynamic environment, where your contributions will directly impact the development of advanced digital systems. If you are passionate about digital design and eager to tackle challenging projects, this is the perfect role for you.

Qualifications

• Experience in digital design engineering with strong debugging skills.
• Proficiency in Verilog, SystemVerilog, C, and C++.

Responsibilities

• Design RTL for memory I/O and develop PHY Digital Architecture.
• Collaborate with engineers to verify new features and conduct digital design.

Skills

Digital Design Engineering

Debugging Firmware

Verilog

SystemVerilog

C

C++

Python

Perl

TCL

Mixed-Signal RTL Design

Education

Bachelor's degree in Computer Engineering

Master's degree in Electrical Engineering

Tools

Simulation Tools

UVM Testbenches

Linux

Windows

Job description

Job Description:

Pay Range: $55/hr - $70/hr

Responsibilities:

• Design RTL for memory I/O.
• Develop PHY Digital Architecture, including pathfinding, coding, verification, and physical implementation.
• Design, implement, and verify PHY link layer in collaboration with Analog and System architects.
• Perform PHY Analog/Digital co-design.
• Conduct digital design and RTL coding.
• Perform Timing Synthesis and drive physical implementation.
• Collaborate with architects, hardware engineers, and firmware engineers to understand and verify new features.
• Develop unit tests.
• Debug design failures, identify root causes, and work with DV and firmware engineers to resolve defects and test issues.

Preferred Experience:

• Experience in digital design engineering.
• Proficiency in debugging firmware and RTL code using simulation tools.
• Experience with UVM testbenches and working in Linux and Windows environments.
• Proficiency in Verilog, SystemVerilog, C, and C++.
• Strong knowledge of Verilog, SystemVerilog, and scripting languages; Python, Perl, and TCL are a plus.
• Knowledge of clocking architectures, synchronization, and CDC methodology.
• Experience with SERDES, DDR, Memory Controller, or MAC Design is preferred.
• Strong understanding of computer organization/architecture.
• Experience with mixed-signal RTL design is a plus.

Academic Credentials:

• Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.