Memory PHY RTL Design Engineer

ZipRecruiter; Boxborough (MA); On-site; USD 80,000 - 100,000; Full time

Job summary

An innovative firm is seeking a Memory PHY RTL Design Engineer to join their dynamic team in Boxborough, MA. This role involves designing and implementing RTL for memory I/O, developing PHY digital architecture, and collaborating with various engineering teams to ensure high-quality designs. The ideal candidate will have a strong background in digital design, proficiency in Verilog and SystemVerilog, and experience with debugging firmware. Join this forward-thinking company to contribute to cutting-edge memory solutions and advance your career in a collaborative environment.

Qualifications

• Proficient in digital design engineering and debugging firmware.
• Experience with Verilog, SystemVerilog, C, and C++.

Responsibilities

• Design and implement RTL for memory I/O and PHY link layer.
• Collaborate with architects and engineers to verify new features.

Skills

Digital Design Engineering

Debugging Firmware

Verilog

SystemVerilog

C

C++

Python

Perl

TCL

UVM Testbenches

Education

Bachelor's degree in Computer Engineering

Master's degree in Electrical Engineering

Job description

Job Description

We are looking for Memory PHY RTL Design Engineer for our client in Boxborough, MA.

Job Title: Memory PHY RTL Design Engineer

Job Location: Boxborough, MA

Job Type: Contract

Pay Range: $55/hr - $70/hr

Responsibilities:

• RTL design for memory I/O.
• Develop PHY Digital Architecture from pathfinding, coding, verification to physical implementation.
• Design, implement, and verify PHY link layer with Analog and System architects.
• Co-design Analog/Digital PHY components.
• Perform digital design and RTL coding.
• Conduct timing synthesis and drive physical implementation.
• Collaborate with architects, hardware engineers, and firmware engineers to understand and verify new features.
• Build unit tests.
• Debug design failures to identify root causes; work with DV and firmware engineers to resolve defects and test issues.

Experience:

• Experience in digital design engineering.
• Proficiency in debugging firmware and RTL code using simulation tools.
• Experience with UVM testbenches and working in Linux and Windows environments.
• Proficient in Verilog, SystemVerilog, C, and C++.
• Knowledge of scripting languages such as Python, Perl, and TCL is a plus.
• Understanding of clocking architectures, synchronization, and CDC methodology.
• Experience with SERDES, DDR, Memory Controller, or MAC design.
• Strong understanding of computer organization/architecture.
• Experience with mixed-signal RTL design is a plus.

Academic Credentials:

• Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.

Company Description: Visit our career site to see all open positions @ http://jobs.cynetsystems.com