Memory IO Validation Engineer (Hybrid)

Intel; Hillsboro (OR); Hybrid; USD 191,000 - 269,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Hybrid work model

Job summary

Intel in Hillsboro, Oregon seeks an experienced validation engineer focused on memory IO interfaces. You will define validation strategies, run system-level tests, and collaborate with architecture, design, and presilicon verification teams to ensure reliability of DDR memory controllers and PHYs.

The role emphasizes MRC requirements, test infrastructure, and debugging to improve yields and margins. Strong Python scripting and knowledge of JEDEC standards are essential; hybrid onsite work

Qualifications

• Bachelor's or Master's in electrical engineering, physics, or related field.
• 5+ years in Memory/DDR technology.
• 5+ years validating and debugging at memory interfaces.
• 5+ years with JEDEC memory protocols and test methodologies.

Responsibilities

• Defines electrical validation strategy for memory IO interfaces to optimize performance.
• Validates circuit analog performance and signal integrity per industry standards.
• Defines MRC requirements and analyzes validation margins and quality.
• Conducts multidisciplinary research for memory IO and mixed signal architectures.
• Develops validation procedures, infrastructure, and margin validation.
• Analyzes returns to improve yields and reduce test escapes.
• Selects components based on specifications and reliability.
• Performs debug to identify root causes and resolves electrical issues.
• Tests interactions between IO design features using validation infrastructure.
• Applies DFT/DFM knowledge to collaborate with teams for test capability.
• Prepares validation specs, evaluates IP, and generates reports.

Skills

Memory/DDR technology

Validation & debug

High-speed I/O

Python scripting

DDRIO/PHY architectures

Education

Bachelors or Master's in electrical engineering, physics, or computer engineering

Tools

Oscilloscopes

Signal generators

BERT

Logic analyzers

Job description

Intel in Hillsboro, Oregon seeks an experienced validation engineer focused on memory IO interfaces. You will define validation strategies, run system-level tests, and collaborate with architecture, design, and presilicon verification teams to ensure reliability of DDR memory controllers and PHYs.

The role emphasizes MRC requirements, test infrastructure, and debugging to improve yields and margins. Strong Python scripting and knowledge of JEDEC standards are essential; hybrid onsite work