Lead MTS Applications Engineer — Hybrid, Bench & Validation

Rambus.com; San Jose (CA); Hybrid; USD 117,000 - 168,000; Full time

Benefits offered by this job

Bonus

Equity

401(k) Matching

Stock Purchase Plan

Medical & Dental Benefits

Time Off Program

Gym Membership

Job summary

Rambus, a premier chip and silicon IP provider, is seeking a Lead MTSApplicationEngineer to join the Memory Interface team in San Jose, CA. The role involves bench validation of I2C/I3C protocols and post-silicon support, with a hybrid work model and opportunities to work with cutting-edge DDR5 enablement devices.

The ideal candidate has 5+ years in post-silicon digital ASIC bench validation, Python-based lab automation, and strong knowledge of I2C/I3C protocols; B.S. or M.S.

Qualifications

• B.S. or M.S. in Electrical Engineering or Computer Engineering.
• 5+ years of post-silicon digital ASIC bench validation experience.
• Experience with I2C/I3C protocols and lab automation in Python.

Responsibilities

• Characterize and validate I2C/I3C protocols on benches.
• Develop Python scripts for bench automation.
• Support customers and provide post-silicon bring-up assistance.
• Collaborate with design, operations, and development teams.

Skills

I2C/I3C protocols

Python scripting

Bench validation

Education

B.S. or M.S. in Electrical or Computer Engineering

Job description

Rambus, a premier chip and silicon IP provider, is seeking a Lead MTSApplicationEngineer to join the Memory Interface team in San Jose, CA. The role involves bench validation of I2C/I3C protocols and post-silicon support, with a hybrid work model and opportunities to work with cutting-edge DDR5 enablement devices.

The ideal candidate has 5+ years in post-silicon digital ASIC bench validation, Python-based lab automation, and strong knowledge of I2C/I3C protocols; B.S. or M.S.