Memory Circuit Architect - Principal Design Engineer

Archer; Boise (ID); On-site; USD 140,000 - 190,000; Full time

Job summary

Micron Technology is seeking a Principal Design Engineer to design and optimize memory circuits, working with cross-functional teams to ensure performance, quality, and timely delivery of next-generation memory solutions.

You will lead schematic blocks, run advanced simulations with SPICE and Verilog, and contribute to silicon validation while advancing memory architecture and CMOS reliability knowledge.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• Experience in semiconductor circuit design, layout, and optimization.
• Proficiency with SPICE and Verilog.
• Ability to interpret product requirements, logic diagrams, and device specifications.
• Experience evaluating and modifying semiconductor devices.

Responsibilities

• Design and optimize memory circuits from gate-level to full chip implementations.
• Lead development of schematic blocks such as memory arrays, control logic, address decode, datapath, and internal test logic.
• Perform advanced circuit simulations using industry tools to validate performance.
• Drive architectural decisions related to power, speed, die area, and overall circuit performance.
• Collaborate with technology development and business units to define design rules, device requirements, and validation strategies.

Skills

Circuit design

SPICE

Verilog

Device analysis

AI in design

Memory architecture

CMOS reliability

Education

Bachelor's degree in Electrical/Computer Engineering

Master's or PhD in Electrical Engineering

Tools

Verification tools

CAD tools

Job description

Micron Technology is seeking a Principal Design Engineer to design and optimize memory circuits, working with cross-functional teams to ensure performance, quality, and timely delivery of next-generation memory solutions.

You will lead schematic blocks, run advanced simulations with SPICE and Verilog, and contribute to silicon validation while advancing memory architecture and CMOS reliability knowledge.