Memory Circuit Architect

Mirafra Technologies; Austin (TX); On-site; USD 140,000 - 210,000; Full time

Job summary

Mirafra Technologies in Austin, Texas is seeking an experienced memory design engineer to analyse architectures, design memory macros, and ensure reliable silicon through rigorous simulation and verification. The role involves transistor-level design, gate-level blocks, and integration of post-layout checks within a robust characterization flow.

You will develop automation scripts, work with SPICE simulators, and contribute to memory models and test plans to correlate silicon with simulations.

Qualifications

• Strong expertise in development of memory compilers and custom macros (SRAMs, register-files, ROMs, multi-ports).
• Deep understanding of transistor-level circuit behavior and device physics.
• Proficiency in memory behavioural and physical models; test setups and silicon debugging.

Responsibilities

• Analyse memory architectures and highlight tradeoffs.
• Design and build memory/circuit blocks at gate/transistor level.
• Simulate and analyse circuit designs using transistor-level simulators.
• Extract layout and perform post-layout simulations and verification.
• Floorplan physical implementation and leafcell layout integration.
• Integrate characterization flow to extract timing and power information.
• Develop scripts to automate characterization flow, simulations, and verification.
• Specify and verify memory behavioural and physical models.
• Document design specifications, behavioural descriptions, and timing diagrams.
• Specify silicon test plan and correlate silicon to simulation data.

Skills

Memory compiler design

Transistor-level circuit analysis

Timing and power analysis

DFT and chip integration

Automation scripting

Leadership and collaboration

Memory models

Tools

SPICE simulators

EDA scripting

Job description

Mirafra Technologies in Austin, Texas is seeking an experienced memory design engineer to analyse architectures, design memory macros, and ensure reliable silicon through rigorous simulation and verification. The role involves transistor-level design, gate-level blocks, and integration of post-layout checks within a robust characterization flow.

You will develop automation scripts, work with SPICE simulators, and contribute to memory models and test plans to correlate silicon with simulations.