Low Power ASIC Verification Engineer — New Grad (Equity)

NVIDIA Corporation; Santa Clara (CA); On-site; USD 100,000 - 190,000; Full time

Benefits offered by this job

Equity and benefits

Job summary

NVIDIA is hiring a New College Grad 2026 for the Low Power Design/Verification ASIC Engineer role in Santa Clara, CA. You will work with the Low Power DV team to architect and develop testbenches, test plans, and power management verification for NVIDIA products including GPUs and SoCs.

You will collaborate across architecture, design, and software groups to implement DV methods, leverage EDA tools, and contribute to power-aware verification strategies.

Qualifications

• BS, MS or PhD in Electrical or Computer Engineering or equivalent experience.
• Understanding of low power design techniques (multi VT, clock gating, power gating, DVFS).
• Strong understanding of GPU architecture and power management DV techniques.
• Proficient with Verilog/SystemVerilog; knowledge of UVM.
• Experience with debugging tools like Verdi and SV-based verification.

Responsibilities

• Architect/develop testbench, infrastructure and test plans to verify power management solutions.
• Collaborate with Low Power Architecture, Design and Software teams to understand features.
• Improve power-aware DV methodologies and influence EDA vendors to improve simulation/debug efficiency.

Skills

Verilog/SystemVerilog

UVM knowledge

Power management concepts

Education

BS/MS/PhD in Electrical or Computer Engineering

Tools

Incisive Low-Power

Synopsys VCS NLP

Verdi

Job description

NVIDIA is hiring a New College Grad 2026 for the Low Power Design/Verification ASIC Engineer role in Santa Clara, CA. You will work with the Low Power DV team to architect and develop testbenches, test plans, and power management verification for NVIDIA products including GPUs and SoCs.

You will collaborate across architecture, design, and software groups to implement DV methods, leverage EDA tools, and contribute to power-aware verification strategies.