Low Power ASIC Engineer - New College Grad 2026

NVIDIA Gruppe; Santa Clara (CA); On-site; USD 100,000 - 166,750; Full time

Benefits offered by this job

Equity

Additional benefits

Job summary

NVIDIA Gruppe is seeking a Low Power Design/Verification ASIC Engineer for New College Grad 2026 in Santa Clara, California. This role involves collaboration with architecture, design, and software teams to establish power-management solutions for NVIDIA’s advanced products.

Ideal candidates will hold a relevant degree and possess knowledge of low-power design techniques and processor architecture. The position offers a competitive salary range of $100,000–$166,750 for Level 1 and $116,000–$189,750 for Level 2, alongside equity and additional benefits.

Qualifications

• Recently completed a BS, MS, or PhD in Electrical or Computer Engineering, or equivalent experience.
• Understanding of low-power design techniques such as multi-VT, clock gating, and dynamic voltage–frequency scaling (DVFS).
• Fluent in Verilog and SystemVerilog.

Responsibilities

• Architect and develop testbenches, infrastructure, and test plans to verify power-management solutions.
• Collaborate with teams to understand next-generation features.
• Improve power-aware Design Verification methodologies.

Skills

Low-Power Design Techniques

Processor Architecture

Debug Skills

Verilog

SystemVerilog

Python

Education

BS, MS, or PhD in Electrical or Computer Engineering

Tools

Incisive Low-Power

Synopsys VCS NLP

Verdi

Job description

Position Overview

We are looking for a Low Power Design/Verification ASIC Engineer – New College Grad 2026. The engineer will work with Low Power Architecture, Design, and Software teams to develop and verify power‑management solutions for NVIDIA’s GPU, SOC, and AI products.

Responsibilities

• Architect and develop testbenches, infrastructure, and test plans to verify power‑management solutions.
• Collaborate closely with Low Power Architecture, Design, and Software teams to understand next‑generation features.
• Bring creative ideas to improve power‑aware Design Verification methodologies and influence EDA vendors to enhance simulation and debug efficiencies.

Qualifications

• Recently completed a BS, MS, or PhD in Electrical or Computer Engineering, or equivalent experience.
• Understanding of low‑power design techniques such as multi‑VT, clock gating, power gating, block activity power, and dynamic voltage–frequency scaling (DVFS).
• Strong understanding of processor architecture (GPU experience a plus) and related power‑management design/Verification techniques.
• Experience with Incisive Low‑Power or Synopsys VCS NLP.
• Strong debug skills and experience with Verdi.
• Fluent in Verilog, SystemVerilog, and an understanding of UVM.

Ways to Stand Out

• Prior knowledge of Low Power Architecture, Low Power CV, and deep learning.
• Good understanding of power intent in UPF format.
• Background in Low Power architectures or verification.
• Scripting abilities in Python or Perl, and knowledge of C or C++.
• Experience writing or maintaining scripts or Makefiles that build the simulation program.

Benefits

• Base salary range: $100,000–$166,750 for Level1 and $116,000–$189,750 for Level2, based on location and experience.
• Equity and additional benefits available.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal‑opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law.