Low-Latency Hardware Design Engineer (FPGA/ASIC)

Hudson River Trading; New York (NY); On-site; USD 270,000 - 330,000; Full time

Job summary

Hudson River Trading (HRT) is seeking talented hardware developers in New York to architect and design complex systems on a highly collaborative global team. You will work with FPGA, ASIC, or both, transforming market data and implementing models with RTL-level precision.

Responsibilities include designing and communicating hardware interfaces, analyzing issues, and continuously learning new technologies to advance hardware capabilities.

Qualifications

• Proficiency in SystemVerilog and digital logic design required.
• Strong FPGA/ASIC knowledge or experience with related design flows.
• Familiarity with Linux, C++, and Python is preferred.

Responsibilities

• Contribute to a highly collaborative team to deliver hardware solutions.
• Describe and communicate hardware designs at interface and implementation levels.
• Analyze and fix problems quickly and efficiently.
• Continuously learn and explore new technologies to deepen hardware expertise.
• Challenge teammates and raise the bar for team output.

Skills

SystemVerilog

FPGA/ASIC knowledge

C++

Python

Digital logic design

Computer architecture

Linux

Education

Bachelors/Masters/PhD in CS/CE/EE

Tools

Vendor tool suites

Job description

Hudson River Trading (HRT) is seeking talented hardware developers in New York to architect and design complex systems on a highly collaborative global team. You will work with FPGA, ASIC, or both, transforming market data and implementing models with RTL-level precision.

Responsibilities include designing and communicating hardware interfaces, analyzing issues, and continuously learning new technologies to advance hardware capabilities.