Low-Latency DV Engineer - FPGA/ASIC Verification

Hudson River Trading; New York (NY); On-site; USD 270,000 - 330,000; Full time

Job summary

Hudson River Trading (HRT) is seeking a Design Verification engineer to build testbenches and verification environments for high-performance FPGA/ASIC hardware. You will root-cause RTL bugs, collaborate with designers, and contribute to CI pipelines and tooling in a fast-paced, real-time trading setting.

The team emphasizes open-source involvement with projects like Slang, Verilator, and Cocotb, and welcomes experts who enjoy pushing verification to the next level.

Qualifications

• Bachelor's degree in computer engineering, computer science or a related field.
• Strong debugging and RTL verification experience.
• Proficiency in Python; Cocotb experience preferred; C++ a plus.

Responsibilities

• Creating testbenches and tests for our hardware platform, leveraging a hybrid open-source/proprietary, highly flexible environment.
• Quickly root-cause RTL bugs.
• Collaborating directly with designers for rapid bringup of new projects and debugging of existing designs.
• Managing test suites and continuous integration infrastructure.
• Developing and improving open-source and internal tools.

Skills

Debugging

RTL verification

Python

Cocotb

C++

Education

Bachelor's in Computer Engineering/CS

Tools

Verilator

Slang

Job description

Hudson River Trading (HRT) is seeking a Design Verification engineer to build testbenches and verification environments for high-performance FPGA/ASIC hardware. You will root-cause RTL bugs, collaborate with designers, and contribute to CI pipelines and tooling in a fast-paced, real-time trading setting.

The team emphasizes open-source involvement with projects like Slang, Verilator, and Cocotb, and welcomes experts who enjoy pushing verification to the next level.