Design Verification Engineer - FPGA/ASIC Innovator

Hudson River Trading; New York (NY); On-site; USD 175,000 - 250,000; Full time

Job summary

Hudson River Trading (HRT) is seeking experienced Design Verification engineers to build verification environments for FPGA/ASIC platforms. You will craft testbenches, debug RTL issues, and collaborate directly with designers for rapid bringup of new projects in a fast-paced trading environment.

The ideal candidate has 2+ years in RTL functional verification, strong SystemVerilog/UVM knowledge, and experience with Python. Familiarity with Verilator or Cocotb is a plus.

Qualifications

• Bachelor’s degree in computer science, electrical engineering, or related field.
• 2+ years of RTL functional verification experience for FPGA or ASIC.
• Strong debugging and analytical skills.
• Familiarity with SystemVerilog and UVM.
• Experience with Python and open-source verification tools.

Responsibilities

• Create testbenches and tests for hardware platform in a hybrid environment.
• Root-cause RTL bugs quickly and efficiently.
• Collaborate with designers for rapid bringup of new projects.
• Manage test suites and CI infrastructure.
• Develop and improve open-source and internal tools.

Skills

Debug & analytics

RTL verification

Code & coverage analysis

SystemVerilog & UVM

Python

Verilator & Cocotb

C++

Education

Bachelor’s degree in CS/EE or related field

Tools

Verilator

Cocotb

UVM

Python

Job description

Hudson River Trading (HRT) is seeking experienced Design Verification engineers to build verification environments for FPGA/ASIC platforms. You will craft testbenches, debug RTL issues, and collaborate directly with designers for rapid bringup of new projects in a fast-paced trading environment.

The ideal candidate has 2+ years in RTL functional verification, strong SystemVerilog/UVM knowledge, and experience with Python. Familiarity with Verilator or Cocotb is a plus.