Lead Silicon Failure Analysis & Yield Improvement

Google LLC; San Diego (CA); On-site; USD 192,000 - 278,000; Full time

Job summary

Google LLC is seeking a Silicon Failure Analysis Lead to drive end-to-end failure analysis for SOCs integrated into mobile devices, tablets and laptops. You will partner with Design, Test, Process Technology, Yield and Reliability teams to isolate root causes and push for robust DFY practices and yield improvements.

You will lead FA activities from silicon to package, including ATE, ATPG/MBIST, curve tracing, non-destructive analysis, and Physical/Electrical Failure Analysis, shaping

Qualifications

• Bachelor's degree in Electrical Engineering or related field or equivalent practical experience.
• 10 years of experience in SoC (System on Chip) Failure Analysis.
• Experience operating failure analysis equipment for performing Electrical Fault Isolation (EFI) and using Automated Test Equipment (ATE) with data from Design for Test (DFT) diagnosis tools.

Responsibilities

• Lead end-to-end Failure Analysis for yield, reliability and field failures.
• Drive root-cause analysis from silicon to package in collaboration with cross-functional teams (Design, Product, Test, Process Technology, Yield, Quality).
• Coordinate with external foundry partners and OSATs to align and enable upstream and downstream yield learning.
• Deliver actionable insights to improve Design for Yield (DFY) practices and manufacturing ramps.

Skills

Electrical Engineering

SoC Failure Analysis

EFI (Electrical Fault Isolation)

ATE data from DFT

Python

C

Java

Collaboration with wafer fabrication/‑

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree or PhD in Electrical/Computer Engineering or Computer Science

Tools

Siemens Tessent

Advantest 93k

Job description

Google LLC is seeking a Silicon Failure Analysis Lead to drive end-to-end failure analysis for SOCs integrated into mobile devices, tablets and laptops. You will partner with Design, Test, Process Technology, Yield and Reliability teams to isolate root causes and push for robust DFY practices and yield improvements.

You will lead FA activities from silicon to package, including ATE, ATPG/MBIST, curve tracing, non-destructive analysis, and Physical/Electrical Failure Analysis, shaping