Senior Die-Level FA Engineer – Yield & Debug Lead

NVIDIA Gruppe; Santa Clara (CA); On-site; USD 144,000 - 264,500; Full time

Benefits offered by this job

Equity

Comprehensive benefits package

Job summary

NVIDIA is seeking a Senior Failure Analysis Engineer in Santa Clara to drive die-level logic fault localization for advanced semiconductor devices. You will work with Design, Test, and DFT teams to identify root causes, accelerate yield improvements, and ensure top product quality.

Responsibilities include hands-on FA, Advantest 93K testing, DFT interpretation, and collaboration across engineering groups to resolve yield, performance, and reliability challenges.

Qualifications

• MS degree in Electrical Engineering, Materials Science, Physics or related field.
• 5+ years hands-on semiconductor failure analysis experience.
• Proficient with Advantest 93K test platform.
• Strong understanding of DFT and logic fault localization.
• Experience with photon/laser-based techniques (LFI) is a plus.

Responsibilities

• Die-level logic fault localization and root cause analysis.
• ATE testing and debugging; set up test loops for LVP/SDL.
• Collaborate with DFT, Product, Test, and Foundry teams to resolve issues.
• Lead cross-functional efforts to improve yield and reliability.

Skills

5+ years semiconductor FA

Advantest 93K

DFT knowledge

LFI techniques

Teradyne Ultraflex Plus (bonus)

Education

MS degree in Electrical Engineering, Materials Science, Physics

Tools

Advantest 93K

Teradyne Ultraflex Plus

Job description

NVIDIA is seeking a Senior Failure Analysis Engineer in Santa Clara to drive die-level logic fault localization for advanced semiconductor devices. You will work with Design, Test, and DFT teams to identify root causes, accelerate yield improvements, and ensure top product quality.

Responsibilities include hands-on FA, Advantest 93K testing, DFT interpretation, and collaboration across engineering groups to resolve yield, performance, and reliability challenges.