Silicon Failure Analysis Lead

Google LLC; San Diego (CA); On-site; USD 192,000 - 278,000; Full time

Job summary

Google LLC is seeking a Silicon Failure Analysis Lead to drive end-to-end failure analysis for SOCs integrated into mobile devices, tablets and laptops. You will partner with Design, Test, Process Technology, Yield and Reliability teams to isolate root causes and push for robust DFY practices and yield improvements.

You will lead FA activities from silicon to package, including ATE, ATPG/MBIST, curve tracing, non-destructive analysis, and Physical/Electrical Failure Analysis, shaping

Qualifications

• Bachelor's degree in Electrical Engineering or related field or equivalent practical experience.
• 10 years of experience in SoC (System on Chip) Failure Analysis.
• Experience operating failure analysis equipment for performing Electrical Fault Isolation (EFI) and using Automated Test Equipment (ATE) with data from Design for Test (DFT) diagnosis tools.

Responsibilities

• Lead end-to-end Failure Analysis for yield, reliability and field failures.
• Drive root-cause analysis from silicon to package in collaboration with cross-functional teams (Design, Product, Test, Process Technology, Yield, Quality).
• Coordinate with external foundry partners and OSATs to align and enable upstream and downstream yield learning.
• Deliver actionable insights to improve Design for Yield (DFY) practices and manufacturing ramps.

Skills

Electrical Engineering

SoC Failure Analysis

EFI (Electrical Fault Isolation)

ATE data from DFT

Python

C

Java

Collaboration with wafer fabrication/‑

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree or PhD in Electrical/Computer Engineering or Computer Science

Tools

Siemens Tessent

Advantest 93k

Job description

X In most instances, this position requires in-person interviews as part of the hiring process.

• Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
• 10 years of experience in SoC (System on Chip) Failure Analysis.
• Experience operating failure analysis equipment for performing Electrical Fault Isolation (EFI) and using Automated Test Equipment (ATE) with data from Design for Test (DFT) diagnosis tools.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field.
• Experience with Siemens Tessent tools for Design for Test (ATPG, MBIST, diagnosis) and ATE platforms such as Advantest 93k.
• Experience modifying digital test programs and test patterns for failure analysis debug.
• Experience with scripting languages such as Python, C, or Java.
• Experience collaborating with wafer fabrication or OSAT (Outsourced Semiconductor Assembly and Test) vendors.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As Silicon Failure Analysis Lead, you will help integrate SOC technologies into mobile phones, tablets and laptops. You will work with different product disciplines (Design, Product, Test, Process Technology, Yield, Quality and Reliability) to accurately determine the root cause of failures, with the aim of developing advanced, high quality, cost effective and reliable Individual Contributor (ICs).
The Failure Analysis (FA) lead will be responsible for all aspects of failure analysis with respect to Silicon Quality and Reliability Engineering activities, engaging in debug activities from the silicon to the entire package. As a technical leader, you will collaborate with cross-functional teams to drive end-to-end Failure Analysis for yield, reliability and field failures. You will have experience in all aspects of failure analysis: ATE and system level testing, diagnostics, Design for Test (ATPG/MBIST), curve tracing, non-destructive analysis (3D X-ray, CSAM, optical inspection), sample preparation, Electrical FA (Photon/Thermal Emission and Laser-based techniques) and Physical Failure Analysis.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As Silicon Failure Analysis Lead, you will help integrate SOC technologies into mobile phones, tablets and laptops. You will work with different product disciplines (Design, Product, Test, Process Technology, Yield, Quality and Reliability) to accurately determine the root cause of failures, with the aim of developing advanced, high quality, cost effective and reliable Individual Contributor (ICs).
The Failure Analysis (FA) lead will be responsible for all aspects of failure analysis with respect to Silicon Quality and Reliability Engineering activities, engaging in debug activities from the silicon to the entire package. As a technical leader, you will collaborate with cross-functional teams to drive end-to-end Failure Analysis for yield, reliability and field failures. You will have experience in all aspects of failure analysis: ATE and system level testing, diagnostics, Design for Test (ATPG/MBIST), curve tracing, non-destructive analysis (3D X-ray, CSAM, optical inspection), sample preparation, Electrical FA (Photon/Thermal Emission and Laser-based techniques) and Physical Failure Analysis.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits
Learn more about benefits at Google .

• Drive yield, reliability, and return merchandise authorization (RMA) failure analysis through fault isolation and physical failure analysis.
• Lead systematic efforts to eliminate yield detractors, accelerate yield ramps, reduce defective parts per million (DPPM), and lower operational costs.
• Collaborate with external foundry partners and OSATs to align and enable upstream and downstream yield learning.
• Deliver investigative insights back to design and layout teams to support robust Design for Yield (DFY) practices and manufacturing ramps.
• Oversee the operational readiness and safety compliance of the regional failure analysis laboratories.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionally by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.