Lead Physical Design Engineer — High-Performance PHY/SOC

Apple Inc.; Cupertino (CA); On-site; USD 129,300 - 225,300; Full time

Job summary

Apple Inc. seeks a forward-thinking Physical Design Engineer in Cupertino, CA to lead high-performance PHY design efforts across RTL to GDSII, collaborating with architecture, CAD, timing and logic teams to deliver cutting-edge products.

In this role you will generate constraints, perform block-level P&R, validate clock networks, implement ECOs and contribute to CAD methodologies for correct-by-construction designs, with Apple’s compensation and benefits.

Qualifications

• Bachelor's degree in Electrical Engineering required.
• Experience with high-performance PHY and SOC designs preferred.
• Strong knowledge of physical design fundamentals and LVS/DRC basics.

Responsibilities

• Contribute to physical design from RTL to GDSII.
• Create timing constraints and floorplanning for chip.
• Conduct block/chip level place and route and ECO fixes.
• Support CAD methodologies and chip integration flow.

Skills

PHY design

Floorplanning

Place & Route

Power delivery

RTL/Verilog

CAD/EDA tooling

Education

Bachelor of Science in Electrical Engineering

Job description

Apple Inc. seeks a forward-thinking Physical Design Engineer in Cupertino, CA to lead high-performance PHY design efforts across RTL to GDSII, collaborating with architecture, CAD, timing and logic teams to deliver cutting-edge products.

In this role you will generate constraints, perform block-level P&R, validate clock networks, implement ECOs and contribute to CAD methodologies for correct-by-construction designs, with Apple’s compensation and benefits.