Lead Memory Validation and Calibration Automation Engineer

Ambarella; Northern (KY); Hybrid; USD 152,000 - 179,000; Full time

Job summary

Ambarella in the United States is seeking an ASIC design engineer to own the memory training and calibration code, collect and analyze data from lab testing and customer platforms, and build automation for stability and performance characterization.

You will debug real customer issues with field and internal teams, influence future silicon with data-driven insights, and validate power-saving features across diverse operating conditions.

Qualifications

• 4+ years in memory validation, memory controller design, SoC validation, or related area.
• Hands-on with LPDDR5/5X and LPDDR6; familiarity with JEDEC specs.
• Experience owning or contributing to memory training and calibration code, with C/firmware skills.
• Strong Python for test automation and data analysis; capable of debugging on hardware.
• Comfort with bench instrumentation, protocol analyzers, and logic analyzers; boot and stability failure triage.

Responsibilities

• Own the memory training and calibration code.
• Collect and analyze memory subsystem data from lab testing, customer platforms, and internal validation systems.
• Build automation for memory stability testing, performance characterization, speed binning, and regression analysis.
• Debug real customer issues alongside field teams and internal engineering groups, driving problems from first report to root cause to closure.
• Turn system behavior and failure analysis into insight that measurably improves memory controller robustness and performance.
• Influence future silicon. Propose architectural and design enhancements for next-generation memory controllers, backed by empirical data, customer feedback, and field experience.
• Validate power-saving features, characterizing them against performance, reliability, and power targets across a wide range of real-world use cases.
• Support silicon bring-up, qualification, and production readiness for memory subsystems.

Skills

LPDDR5/5X knowledge

LPDDR6 knowledge

Memory training code

Python for test automation

C/firmware skills

Hardware debugging

Tools

Oscilloscope

Logic analyzers

Protocol analyzers

Bench instrumentation

Job description

Ambarella in the United States is seeking an ASIC design engineer to own the memory training and calibration code, collect and analyze data from lab testing and customer platforms, and build automation for stability and performance characterization.

You will debug real customer issues with field and internal teams, influence future silicon with data-driven insights, and validate power-saving features across diverse operating conditions.