Staff Analog IC Design Engineer for AI Accelerators

Entrada Ventures; Santa Clara (CA); On-site; USD 180,000 - 280,000; Full time

Job summary

d‑Matrix is seeking a Staff Analog Design Engineer to lead analog‑mixed signal IC design for our AI inference accelerators. You will own circuit design from schematic through silicon bring‑up, guiding layout engineers on 7nm and below and ensuring low‑power performance across PVT corners.

You will partner with backend and digital teams, build test benches and models, support silicon bring‑up and characterization, and collaborate with cross‑site colleagues to deliver silicon‑ready designs that

Qualifications

• BS, MS or PhD in Electrical Engineering with 5+ years of relevant experience in high-speed circuit design.

Responsibilities

• Design analog‑mixed signal circuits using Cadence and Synopsys
• Develop schematic-level circuit designs and conduct system-level performance analysis
• Build test benches to support simulation and verification, including Monte Carlo yield analysis across PVT corners
• Guide layout engineers on circuit layout in deep sub‑micron process nodes (7nm and below)
• Partner with backend engineers to integrate design and layout, and provide circuit models for backend verification
• Support testboard design for silicon bring‑up, bench debug, and characterization
• Build scripts to support silicon bring‑up and test feature validation

Skills

High-speed circuit design

Schematic capture

SPICE simulation

Monte Carlo simulation

Cross-functional collaboration

Analytical problem solving

Education

EE degree

Tools

Cadence

Synopsys

MATLAB

Job description

d‑Matrix is seeking a Staff Analog Design Engineer to lead analog‑mixed signal IC design for our AI inference accelerators. You will own circuit design from schematic through silicon bring‑up, guiding layout engineers on 7nm and below and ensuring low‑power performance across PVT corners.

You will partner with backend and digital teams, build test benches and models, support silicon bring‑up and characterization, and collaborate with cross‑site colleagues to deliver silicon‑ready designs that