Principal Physical Verification Engineer

Celero Communications, Inc.; San Jose (CA); Hybrid; USD 150,000 - 250,000; Full time

Job summary

Celero Communications, Inc. in San Jose, CA, is seeking a Principal Physical Verification Engineer to own all aspects of full-chip PV on advanced process nodes. You will collaborate with Analog and Physical Design teams to ensure tapeout readiness and high-quality DRC/LVS results.

The role requires 7+ years of PV experience, expertise with ICV/Calibre, and scripting skills in Tcl/Python. The position offers competitive base salary, strong growth, and exposure to cutting-edge 7nm/5nm tech.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering or related field.
• 7+ years of experience with full-chip verifications.
• Experience with Physical Verification tools such as IC Validator (ICV) and Calibre.
• Ability to assemble a flow to support block/chip level PV.
• Strong floorplanning skills to avoid DRC/LVS issues.
• Automation skills using Tcl, Python, or shell scripting.

Responsibilities

• Lead the full-chip Physical Verification effort.
• Own execution plans and schedules for full-chip PV.
• Drive quality, milestones, and tapeout readiness.
• Collaborate with analog and layout teams to ensure clean integration.
• Support tapeout readiness reviews.

Skills

Full-chip PV

Floorplanning

Automation scripting

Education

Bachelor's or Master's degree in Electrical Engineering or related field

Tools

Synopsys IC Validator (ICV)

Siemens Calibre

Job description

Principal Physical Verification Engineer

San Jose, CA

Celero Communications is a fast-growing semiconductor startup developing high-performance coherent DSP technology for next-generation AI infrastructure. We recently announced a $275M Series C following the validation of the industry's first 2nm coherent DSP silicon. Bloomberg also reported that Alphabet's CapitalG has backed Celero at a $3B valuation. As we continue to grow, we're hiring exceptional talent across the United States, Canada, and Argentina for a variety of exciting opportunities.

We are seeking a Full-Chip Physical Verification Engineer to join our Physical Design team and help deliver complex digital blocks and full-chip implementations in advanced process technologies. This role will own all aspects of Physical Verification execution on advanced TSMC nodes, ensuring design quality, manufacturability, and tapeout readiness. The ideal candidate has successfully completed multiple tapeouts and brings deep expertise in physical verification methodologies, including driving improvements in quality, execution efficiency, and predictable delivery across multiple programs. You will work closely with the Analog Design and Physical Design teams to identify and resolve verification challenges while ensuring designs meet aggressive performance, manufacturability, and schedule objectives.

Key Responsibilities

Team & Project Leadership

• Lead full chip Physical Verification effort
• Own execution plans, schedules for full-chip
• Drive accountability for quality, milestones, and tapeout readiness.
• Conduct full chip and blocks PV checks

Physical Verification Ownership

• Ownership of full chip verification
• Work with internal analog team to ensure clean IP delivery
• Responsible for running and analyzing DRC/ERC/LUP/PERC results
• Experience with using either ICV or Calibre verification tools
• Understanding advance TSMC DRC rules

Cross-Functional Collaboration

• Partner with analog, block, chip top owners to ensure clean floorplan
• Provide early guidance on corner case requirements
• Influence floorplan constraints, hierarchy, and implementation strategy
• Participate in tapeout readiness reviews

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering or related field.
• 7+ years of experience with full-chip verifications

Proven hands-on experience with:

• Physical Verification tools (Synopsys IC Validator (ICV), Siemens Calibre)
• Able to assemble a flow to support block/chip level PV

Strong expertise in:

• Floorplanning to avoid DRC/LVS issues
• Provide guidance to analog IP team to allow for clean integration

Preferred Qualifications

• Experience in advanced technology nodes (7nm, 5nm, 3nm)
• Automation skills using Tcl, Python, or shell scripting

Annual Base Salary Range: $150,000 - $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location)

Voluntary Self-Identification

For government reporting purposes, we ask candidates to respond to the below self-identification survey.Completion of the form is entirely voluntary. Whatever your decision, it will not be considered in the hiringprocess or thereafter. Any information that you do provide will be recorded and maintained in aconfidential file.

As set forth in Celero Communications, Inc.’s Equal Employment Opportunity policy,we do not discriminate on the basis of any protected group status under any applicable law.

If you believe you belong to any of the categories of protected veterans listed below, please indicate by making the appropriate selection.As a government contractor subject to the Vietnam Era Veterans Readjustment Assistance Act (VEVRAA), we request this information in order to measurethe effectiveness of the outreach and positive recruitment efforts we undertake pursuant to VEVRAA. Classification of protected categoriesis as follows:

A "disabled veteran" is one of the following: a veteran of the U.S. military, ground, naval or air service who is entitled to compensation (or who but for the receipt of military retired pay would be entitled to compensation) under laws administered by the Secretary of Veterans Affairs; or a person who was discharged or released from active duty because of a service-connected disability.

A "recently separated veteran" means any veteran during the three-year period beginning on the date of such veteran's discharge or release from active duty in the U.S. military, ground, naval, or air service.

An "active duty wartime or campaign badge veteran" means a veteran who served on active duty in the U.S. military, ground, naval or air service during a war, or in a campaign or expedition for which a campaign badge has been authorized under the laws administered by the Department of Defense.

An "Armed forces service medal veteran" means a veteran who, while serving on active duty in the U.S. military, ground, naval or air service, participated in a United States military operation for which an Armed Forces service medal was awarded pursuant to Executive Order 12985.