Lead FPGA & Embedded Firmware Architect

Eaton Group; Youngsville (NC); On-site; USD 105,000 - 154,000; Full time

Job summary

Eaton in Youngsville, NC is seeking a Lead Embedded Firmware & FPGA Engineer to drive architecture, design, verification and release of FPGA-based power management solutions. You will collaborate with global teams on SiC-based three-phase systems for mission-critical loads such as data centers.

Responsibilities include RTL development in Verilog/SystemVerilog/VHDL, FPGA integration with microcontrollers and DSPs, testbenches, timing analysis, and design reviews to ensure robust, scalable

Qualifications

• Bachelor’s degree in Electrical/Electronics/Computer Engineering with 5 years embedded firmware or software experience.
• Master’s degree with 4 years experience, or PhD with required lab work.
• Experience with synthesizable RTL using VHDL, Verilog, and/or SystemVerilog.
• Experience with FPGA design workflows including RTL development, simulation, synthesis, and timing analysis.

Responsibilities

• Architect, develop, verify, test, and release FPGA-based designs for new products.
• Translate system requirements into FPGA architecture and detailed design specs.
• Design, develop, review, and maintain RTL using Verilog, SystemVerilog, and/or VHDL.
• Develop testbenches, perform RTL simulation, and ensure timing closure.

Skills

FPGA design

Verilog/SystemVerilog

RTL development

Embedded firmware

SiC power electronics

Cross-functional teamwork

Education

Bachelor's degree

Master's degree

PhD

Tools

Intel Quartus

ModelSim/Questa

Vivado

Job description

Eaton in Youngsville, NC is seeking a Lead Embedded Firmware & FPGA Engineer to drive architecture, design, verification and release of FPGA-based power management solutions. You will collaborate with global teams on SiC-based three-phase systems for mission-critical loads such as data centers.

Responsibilities include RTL development in Verilog/SystemVerilog/VHDL, FPGA integration with microcontrollers and DSPs, testbenches, timing analysis, and design reviews to ensure robust, scalable