Lead FinFET Data Converter IC Design Engineer

Encore Semi Llc; San Diego (CA); On-site; USD 150,000 - 180,000; Full time

Benefits offered by this job

PTO 15 days

Holidays 10

Medical benefits 80% covered

Dental & Vision 50% covered

Life Insurance

FSA / HAS

401k retirement plan

Tuition reimbursement

Employee Assistance Program

Job summary

Encore Semi LLC in San Jose and San Diego seeks a Senior/Lead Data Converter IC Design Engineer (FinFET) to architect and tape out high-speed ADC/DACs in 7nm–3nm FinFET processes. You will own the full design cycle from system architecture to post-silicon validation for HPC, AI, and communications hardware.

The role requires 10+ years in high-speed data converter design, FinFET node expertise, and strong Cadence tool proficiency.

Qualifications

• MS/PhD in Electrical Engineering or related field.
• 10+ years of hands‑on high‑speed data converter design and silicon tape‑outs.
• Experience with FinFET nodes (3nm/5nm/7nm).
• Knowledge of FinFET constraints (fin quantization, g m / g ds, 3D RC extraction).
• Familiarity with Cadence Virtuoso, Spectre/PrimeSim, and Calibre PEX/Quantus.

Responsibilities

• Architect and design multi-GS/s ADC/DAC architectures (Time-Interleaved SAR, Pipeline, Flash, or RF-DACs).
• Deliver transistor-level circuits (track-and-hold, comparators, low-jitter clock paths, bias networks) in 7nm–3nm FinFET processes.
• Implement background/foreground digital calibration for offset, gain, timing skew, and linearity.
• Supervise layout to mitigate layout-dependent effects (LDE), parasitics, electromigration, and self-heating.
• Lead post-silicon lab bring-up, bench testing, and model-to-hardware correlation.

Skills

FinFET design expertise

High-speed data converter design

Silicon tape-out experience

Education

M.S. or Ph.D. in Electrical Engineering or related field

Tools

Cadence Virtuoso

Spectre/PrimeSim

Calibre PEX/Quantus

Job description

Encore Semi LLC in San Jose and San Diego seeks a Senior/Lead Data Converter IC Design Engineer (FinFET) to architect and tape out high-speed ADC/DACs in 7nm–3nm FinFET processes. You will own the full design cycle from system architecture to post-silicon validation for HPC, AI, and communications hardware.

The role requires 10+ years in high-speed data converter design, FinFET node expertise, and strong Cadence tool proficiency.