DFT Engineer

Mirafra Technologies; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Mirafra Technologies is seeking an experienced DFT engineer with 8-15 years of hands-on experience in scan, ATPG, and JTAG for complex SoCs. You will debug, optimize and validate DFT flows across block and chip levels, using Verilog RTL and industry tools like VCS and Verdi.

The role requires proficiency in Synopsys DFT tools (Testmax, Tetramax, DC, FC) and scripting (Python, TCL). Strong problem solving and self-motivation are essential.

Qualifications

• B.Tech / M.Tech with 8-15 years of experience in DFT.
• Strong knowledge of DFT architecture, methodologies and structural debug concepts: JTAG.
• Experience in handling DFT of large multi multimillion gate multi clock domain SoCs.
• Hands-on experience in SCAN, ATPG and JTAG implementation at block and chip level.
• Knowledge of Verilog RTL and hands-on experience in using simulators and waveform debugging tools such as VCS and Verdi.
• Hands on experience in using Synopsys DFT tools like Testmax, Tetramax, DC & FC.
• Experience in post silicon debug.
• Knowledge of Python, Shell scripting, Makefiles, TCL.
• Excellent problem solving skills and highly self-motivated.

Responsibilities

• -Execute Scan insertion, Scan DRC check and debug. review DRC reports, debug and resolve
• -Tmax pattern generation, Optimize ATPG patterns and improve Fault coverage, check and debug ATPG DRCs
• -Knowledge of Codec/EDT architecture, OCC working in different modes, DFT mode clockings
• -to debug complex scan issues indepedently/with minimum supervision
• -Verify ATPG tests in Zero delay and SDF annotated simulations
• -Debug simulation failures in VCS, Verdi and other simulators
• -Work on pattern porting, contribute to DFT methodology and flow automation
• -Post silicon validation and debug; Ablity to support ATE silicon debugs

Skills

DFT architecture

ATPG debugging

SCAN

JTAG

Verilog RTL

Problem solving

Python

Shell scripting

Makefiles

Education

B.Tech / M.Tech (preferred)

Tools

Synopsys Testmax

Tetramax

DC

FC

VCS

Verdi

Waveform simulators

Job description

• -Execute Scan insertion, Scan DRC check and debug. review DRC reports, debug and resolve

DRCs

• -Tmax pattern generation, Optimize ATPG patterns and improve Fault coverage, check and
• debug ATPG DRCs
• -Knowledge of Codec/EDT architecture, OCC working in different modes, DFT mode clockings
• - to debug complex scan issues indepedently/with minimum supervision
• -Verify ATPG tests in Zero delay and SDF annotated simulations
• -Debug simulation failures in VCS, Verdi and other simulators
• -Work on pattern porting, contribute to DFT methodology and flow automation
• -Post silicon validation and debug; Ablity to support ATE silicon debugs

Requirements:

• -B.Tech / M.Tech (preferred) with 8-15 years of experience in DFT
• -Strong knowledge of DFT architecture, methodologies and structural debug concepts : JTAG,
• -Experience in handling DFT of the large multi multimillion gate multi clock domain SoCs
• -Hands on experience in SCAN, ATPG and JTAG implementation at block and chip level
• -Knowledge of Verilog RTL and hands on experience in using simulators and waveform
• debugging tools such as VCS and Verdi
• -Hands on experience in using Synopsys DFT tools like Testmax, Tetramax, DC & FC
• -Experience in post silicon debug
• -Knowledge of Python, , Shell scripting, Makefiles, TCL
• -Excellent problem solving skills and highly self-motivated