Lead Design Verification

Mirafra Technologies; San Jose (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

A leading company in the semiconductor manufacturing sector is seeking a Design Specialist in San Jose, CA. The role involves developing verification methodologies and testbenches for digital and mixed-signal blocks, requiring a solid background in ASIC design verification. Candidates with extensive experience in SystemVerilog and UVM testbench development are encouraged to apply. This full-time position offers a dynamic work environment and opportunities for professional growth.

Qualifications

• 10+ years of ASIC design verification experience for US-based lead.
• 2-5 years of work or academic experience in ASIC design verification for other engineers.
• Proficient in handling technical tasks independently.

Responsibilities

• Develop verification methodology and testbenches for digital and mixed-signal blocks.
• Design test plans and conduct coverage analysis for IP blocks.
• Ensure closure for parallel link and SerDes IP blocks.

Skills

SystemVerilog

UVM testbench development

Programming

Scripting

Version control (Git)

Education

BSc or MSc in Electrical Engineering

Computer Engineering

Tools

NCSIM

VCS

ModelSim

Job description

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Responsibilities:

• Develop verification methodology and testbenches for digital and mixed-signal blocks.
• Design test plans, conduct coverage analysis, and ensure closure for parallel link and SerDes IP blocks, as well as on-chip interconnects.

Basic Qualifications:

• BSc or MSc in Electrical Engineering, Computer Engineering, or related fields.
• Experience:
• US-based lead should have 10+ years of ASIC design verification experience.
• Other engineers should have 2-5 years of work or academic experience in ASIC design verification.
• Proven ability to handle various technical tasks independently and complete projects.
• Proficient in SystemVerilog and UVM testbench development for complex digital and PHY blocks, including AMS and WREAL modeling.
• Skilled in pre-synthesis and post-place-and-route functional verification using tools like NCSIM, VCS, ModelSim.
• Programming or scripting experience.
• Experience with version control software such as Git.

Preferred Qualifications:

• Experience with digital designs involving multiple clock domains and clock dividers.
• Verification experience with SerDes IP interfaces in complex SoC environments.
• Knowledge of verification for PCS, PMA SerDes layers, and internal SerDes digital backends.
• Experience with HBM memory interface verification (PHY and controller).
• Familiarity with formal model equivalence checking tools and methodologies.

Programming experience in Python is a plus.

Seniority Level:

• Mid-Senior level

Employment Type:

• Full-time

Job Function:

• Engineering, Design, and Information Technology

Industries:

• Computer Hardware Manufacturing, Semiconductor Manufacturing, Software Development

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