Lead Design Engineer

Cadence Design Systems, Inc.; San Jose (CA); Sur place; USD 120 000 - 180 000; Plein temps

Résumé du poste

Cadence Design Systems, Inc. in San Jose is seeking a hardware verification engineer to implement and verify high‑capacitance Palladium and Protium SOC tape-out. You will contribute to RTL synthesis, clock tree building, timing closure and cross‑functional design reviews.

The role requires strong Linux scripting skills, experience with Cadence tools, and familiarity with next‑gen process nodes. A collaborative, innovative environment supports career growth and impact.

Qualifications

• Requires a BS in Electrical Engineering with 5+ years of experience or MS with 3+ years.
• Hands-on experience with Cadence tools such as Innovus, Tempus, QRC, Voltus and Pegasus.
• Experience with advanced nodes like 5nm, 3nm, and 2nm.
• Proficiency with Linux, shell scripting, Perl, TCL, and Python.
• Knowledge of PCIe, DDR, LPDDR, SRAM, UCIe interfaces.

Responsabilités

• Implement, verify, and ensure timing closure for Palladium and Protium SOC tape-out.
• Work on RTL synthesis and floorplanning.
• Build clock trees and perform optimizations.
• Close timing, IR drop and physical verification.
• Review and document designs for tape-out and interface with FE RTL and BE verification teams.

Connaissances

Hardware verification

Troubleshooting

Cross-functional collaboration

Scripting

Formation

BS in Electrical Engineering

MS in Electrical Engineering

Outils

Innovus

Tempus

QRC

Voltus

Pegasus

Description du poste

CARY

SAN JOSE

Full time

R55673

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We offer amazing opportunities to grow, no matter where you are in your career.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.

• Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.

• The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success

• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests

• You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

Job Responsibility

Palladium and Protium are high-capacitive, high-performance hardware assisted verification for complexed System‑On‑Chip (SOC). This role is to implement, verify, timing closure to tape out Palladium and Protium SOCs.

• Work on RTL synthesis and floorplanning

• Build clock trees and perform optimizations

• Close timing, IR drop and physical verification

• Review and Document designs for taping out

• Interface with Front End RTL design teams and Back End Verification teams

Position Requirements/Qualifications:

• BS degree in Electrical Engineering with a minimum of 5 years of experience OR MS with a minimum of 3 years of experience

• Experience with Cadence tools such as Innovus, Tempus, QRC, Voltus and Pegasus

• Experience with advanced technologies like 5nm, 3ns and 2nm nodes

• Experience using Linux servers, Script development using Shell/Perl/TCL/Python

• Detailed knowledge about industry standard interfaces such as PCI Express, DDR, LPDDR, SRAM, UCIe, etc.

  We’re doing work that matters. Help us solve what others can’t.

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Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadense is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Cadense is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.