Lead CPU Micro-Architect & RTL Engineer (Verilog)

NUVACORE; Santa Clara (CA); Presencial; USD 180 000 - 240 000; Tempo integral

Resumo da oferta

NUVACORE is building a high-performance, low-power CPU for next-generation compute workloads. You will contribute to micro-architecture, RTL design, and verification across fetch, decode, execute, and memory units.

In this role, you will collaborate with performance modeling, PD, and verification teams to meet strict power, timing, and area goals while supporting modern AI tooling for RTL coding.

Qualificações

• BS or MS in CS/EE with 15+ years leading CPU or 7+ years IC experience preferred.
• Experience coding in Verilog and debugging/simulation.
• Solid understanding of logic and physical design impacts on timing, power, and area.
• Experience with RISC-V, ARM64, or x86 ISA and related micro-architectural choices.

Responsabilidades

• Micro-architecture development and specification from performance-driven design strategy.
• RTL design for power, performance, area and timing goals; write flexible, scalable RTL.
• Assist verification team with testbench development, formal methods, and simulation/emulation.
• Explore performance strategies with architecture and verification teams to ensure RTL meets targets.
• Work with PD to implement and verify physical design requirements and timing/power/area optimizations.

Conhecimentos

Verilog

RTL design

Debugging & simulation

AI RTL tools

ISA experience (RISC-V/ARM/x86)

Power and timing optimization

CPU microarchitecture

C/C++

Formação académica

BS or MS in CS/EE

Ferramentas

Verilog simulators

EDA tools

Formal verification tools

Automation/CI tools

Descrição da oferta de emprego

NUVACORE is building a high-performance, low-power CPU for next-generation compute workloads. You will contribute to micro-architecture, RTL design, and verification across fetch, decode, execute, and memory units.

In this role, you will collaborate with performance modeling, PD, and verification teams to meet strict power, timing, and area goals while supporting modern AI tooling for RTL coding.