Senior CPU Micro-Architect & RTL Lead Engineer

NUVACORE

United States

On-site

USD 180,000 - 240,000

Full time

2 days ago
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Job summary

Nuvacore is building a high-performance, low-power CPU for next-generation workloads. We seek a CPU Micro-Architect/RTL Engineer to drive micro-architectural specs, write RTL, assist verification, and optimize performance and physical design across power and area.

Join a team shaping instructions fetch through memory systems, with opportunities to influence timing, power, and reliability while leveraging modern Verilog and AI-assisted RTL tooling.

Qualifications

  • BS or MS in a relevant field with 15+ years of leads experience and 7+ years in CPU design.
  • Experience coding in Verilog, debugging and simulation, with AI tools for RTL coding.
  • Solid understanding of logic and physical design and their impact on timing, power and area.
  • Experience with RISC-V, ARM64 or x86 ISA and related micro-architecture decisions.

Responsibilities

  • Micro-architecture development and specification from performance driven design strategy.
  • RTL design to meet power, performance, area and timing goals with scalable configurations.
  • Support verification with testbench development, formal methods, and simulations.
  • Explore performance and verify RTL meets targeted performance with peers.
  • Collaborate on physical design to meet timing, power, area, DFT and reliability targets.

Skills

Verilog
Debugging
Simulation
AI tools for RTL
Logic design
Physical design
ISA knowledge
C/C++ knowledge

Education

BS or MS in a relevant field

Tools

C
C++
Perl
Python

Job description

Nuvacore is building a high-performance, low-power CPU for next-generation workloads. We seek a CPU Micro-Architect/RTL Engineer to drive micro-architectural specs, write RTL, assist verification, and optimize performance and physical design across power and area.

Join a team shaping instructions fetch through memory systems, with opportunities to influence timing, power, and reliability while leveraging modern Verilog and AI-assisted RTL tooling.

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