ASIC Verification Engineer – SystemVerilog & UVM

Blue Origin; Hutto (TX); On-site; USD 129,000 - 181,000; Full time

Benefits offered by this job

Stock Options

401(k) with company match

Paid Time Off

Job summary

Blue Origin in the United States is seeking early-career engineers to contribute to Verilog/SystemVerilog design and verification of digital blocks within large SoCs. You will work with senior engineers on testbenches, coverage, and integration of external IP, applying industry verification methodologies.

The role emphasizes collaboration, learning, and applying basic scripting (Python/Perl) for tooling, with opportunities to co-locate with hardware teams.

Qualifications

• BS or MS in Electrical/Computer Engineering or related technical field (completed or in final year).
• Coursework or project experience with Verilog/SystemVerilog RTL design or verification.
• Understanding of digital logic design fundamentals (combinational/sequential logic, FSMs, timing).
• Familiarity with basic verification concepts (testbenches, simulation, coverage).
• Strong problem‑solving skills and attention to detail.
• Effective communication and ability to work in a collaborative team environment.

Responsibilities

• Contribute to Verilog/SystemVerilog design and verification of digital blocks within larger SoCs.
• Support module-level and subsystem-level verification using SystemVerilog/UVM.
• Write test plans and functional coverage definitions under guidance from senior team members.
• Assist with CDC/RDC/LINT checks and clean‑up.
• Participate in code coverage and functional coverage closure activities.
• Help develop assertions, protocol monitors, and scoreboards for testbenches.
• Support integration and verification of external IP (e.g., bus fabrics, standard interfaces).
• Learn and apply industry‑standard verification methodologies (UVM, formal verification basics).
• Debug RTL and testbench issues with guidance from senior engineers.
• Document design intent, verification results, and test coverage.

Skills

Verilog/SystemVerilog

Digital logic

Verification concepts

Problem solving

Communication

Education

BS in Electrical/Computer Engineering

MS in EE/CE or related

Tools

VCS

Questa

Xcelium

Python scripting

Job description

Blue Origin in the United States is seeking early-career engineers to contribute to Verilog/SystemVerilog design and verification of digital blocks within large SoCs. You will work with senior engineers on testbenches, coverage, and integration of external IP, applying industry verification methodologies.

The role emphasizes collaboration, learning, and applying basic scripting (Python/Perl) for tooling, with opportunities to co-locate with hardware teams.