Lead ASIC Verification Engineer for AI Accelerators

Samsung-Semiconductor; San Jose (CA); Presencial; USD 219.000 - 351.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Paid time off

Holidays & sick leave

Fertility care stipend

Caregiver support

Medical travel support

Onsite café & gym

Flexible benefits

Descripción de la vacante

Samsung Semiconductor seeks an experienced ASIC verification engineer to advance memory and AI accelerator projects at our San Jose headquarters or Folsom facility. You will contribute to verification strategy, microarchitecture reviews, and post-silicon debugging, collaborating closely with architects and design teams.

The ideal candidate has 20+ years in ASIC verification, strong UVM, and C++/SystemVerilog skills, with deep knowledge of SoC verification and verification flows.

Formación

• BE (MS preferred) in Computer/Electrical Engineering or Computer Science with 20+ years working experience in ASIC verification preferred.
• Experience in UVM.
• Strong language skills including C++, SystemVerilog.
• Experience in logic and SoC verification from planning to closure.
• Good understanding on verification flows and tools.
• Experience in UCIe, HBM controller, Memory DFT.

Responsabilidades

• Participate in verification strategy and methodology definitions.
• Contribute in micro architecture specification and reviews.
• Responsible for the verification of modules/subsystems of AI accelerators.
• Execute the verification per plan to the closure.
• Work closely with architects and design engineers to define verification requirements, and to close functional and code coverage targets.
• Provide support in post silicon bring up and debug.

Educación

BE (MS preferred) in Computer/Electrical Engineering or Computer Science

Herramientas

UVM

C++

SystemVerilog

SoC verification

verification tools

UCIe

HBM controller

Memory DFT

Descripción del empleo

Samsung Semiconductor seeks an experienced ASIC verification engineer to advance memory and AI accelerator projects at our San Jose headquarters or Folsom facility. You will contribute to verification strategy, microarchitecture reviews, and post-silicon debugging, collaborating closely with architects and design teams.

The ideal candidate has 20+ years in ASIC verification, strong UVM, and C++/SystemVerilog skills, with deep knowledge of SoC verification and verification flows.