Asic Chip Lead-Full Time- Onsite

Technical Link LLC; Brooklyn Park (MN); On-site; USD 145,000 - 205,000; Full time

Job summary

Technical Link LLC in Brooklyn Park, MN is seeking an ASIC Chip Lead to drive RTL and block-level design across the full design flow. This on-site role collaborates with cross-functional teams to meet performance, power, and area targets.

The ideal candidate has 10+ years in ASIC/SoC, strong Verilog/SystemVerilog, and hands-on experience with Synopsys Design Compiler and EDA tools. Mentors engineers and influences design methodologies.

Qualifications

• 10+ years of direct ASIC/SoC design experience.
• Strong RTL design and verification fundamentals.
• Proficiency with Synopsys Design Compiler and EDA tools.

Responsibilities

• Lead architectural design of ASICs from high-level requirements.
• Develop detailed chip specifications and interfaces.
• Own RTL design, synthesis, timing constraints, and place-and-route collaboration.
• Support verification, testbench creation, and design closure issues.
• Mentor junior engineers and participate in design methodologies.

Skills

UNIX/Linux

Shell scripting

C/C++

Python/TCL scripting

Verilog/SystemVerilog

RTL design

EDA tools

Synopsys Design Compiler

RISC architectures

Leadership

Education

Bachelor's or Master's in electrical engineering or computer science

Tools

Synopsys Design Compiler

EDA tools

Job description

Asic Chip Lead-Full Time- Onsite Brooklyn Park, MN

As an ASIC Chip Lead and Design Engineer, you will play a pivotal role in the development of custom-designed Application-Specific Integrated Circuits (ASICs). Your expertise will span the entire chip design lifecycle, from conceptualization to implementation. You’ll collaborate with cross-functional teams, ensuring successful chip development while adhering to performance, power, and area targets. The right candidate will be someone with high aptitude who is currently hands on designing complex digital blocks, with strong knowledge/experience across the complete ASIC/SOC design flow. An ideal candidate will additionally have experience with radiationhardened design, analog/mixed-signal design and EDA, and std-cell library development. Additional duties include the evaluation of customer requirements and estimates of effort/expenses for potential new business, and participation in identifying problems with and improvements to, internal design methodologies.

Essential Duties And Qualifications

Chip Architecture and Development

• Lead the architectural design of ASICs based on high-level requirements and block diagrams.
• Collaborate with system architects to define chip functionality, interfaces, and performance targets.
• Develop detailed specifications for the chip’s components.

RTL Design And Synthesis

• Use Synopsys Design Compiler to create RTL (Register Transfer Level) designs.
• Optimize RTL code for area, power, and performance.
• Implement and verify complex digital blocks.

Constraint Development

• Develop timing constraints for the entire chip.
• Work closely with physical design teams to ensure successful place-and-route.
• Constrain and verify RISC processors within the chip. Optimize processor performance and power efficiency.

Physical Design Collaboration

• Collaborate with physical design teams on floorplanning, placement, and routing.
• Address any design closure issues.

Verification Support

• Work with verification engineers to ensure functional correctness.
• Assist in creating testbenches and verifying the chip’s functionality.

Modern revision-control tools and best-practices in a collaborative, multi-site design community. Proficiency with UNIX/Linux incl. shell scripting, text utilities (e.g. sed, awk, grep), using Modules, high-level programming such as C/C++, PERL/Python/TCL scripting. Proficiency with Windows apps, incl. Word, Excel, PowerPoint, Visio, Project, PDF conversion.

Qualifications

• Bachelors/master’s in electrical engineering/computer science or equivalent.
• 10+ years of direct industry experience with ASIC and/or SoC design.
• Proficiency in Synopsys Design Compiler and other EDA tools.
• Strong understanding of digital design principles.
• Familiarity with RISC architectures (e.g., ARM, MIPS).
• Excellent problem-solving skills and attention to detail.
• A strong background in RTL based digital IC design using Verilog/SystemVerilog Proven track record of first-pass successes.
• A self-starter with the ability to assume leadership roles.
• Ability to work well in a diverse team environment.
• Willingness to Mentor less senior engineers.
• Experience with industry standard development tools and methodologies.

Target Annual Salary

• The US base salary range for this full-time position is $145,000-$205,000.

Location

• Work on-site at the TSS office in Brooklyn Park, MN.