Implementation Lead

Oho Group; San Francisco (CA); On-site; USD 200,000 - 260,000; Full time

Job summary

Stealth Startup, based in San Francisco, seeks an Engineering Leader to drive physical implementation for custom ASICs. You will own end-to-end backend strategies, coordinate with the team, and grow the function to scale high-performance silicon in a fast-moving startup environment.

The role emphasizes hands-on implementation, AI-augmented design flows, and leadership across sign-off and optimization tasks to deliver PPA targets for AI-enabled accelerators.

Qualifications

• 5–10 years of physical-design experience, with tape-out of large-die SoCs or compute subsystems.
• Hands-on experience with AI-enabled design-optimisation tools integrated into production flows.
• Strong understanding of reinforcement-learning principles for EDA and layout density.
• Expertise in physical sign-off including STA, DRC, LVS and EM/IR on advanced nodes.

Responsibilities

• Deliver physical implementation for high-throughput, low-latency accelerators optimized against KPIs.
• Define and drive layout strategy for IP, high-bandwidth interfaces, large on-chip SRAM and register structures.
• Lead deployment of AI-driven design-optimisation engines to automate macro placement and timing/power optimization.
• Address physical-design challenges for AI workloads including IR-drop, thermal-density and clock-tree synthesis.
• Apply reinforcement-learning principles across backend implementation stages to drive design optimisation.

Skills

Physical design

Python

Reinforcement learning

Tcl

Tools

AI-enabled design tools

EDA/Sign-off tools

Job description

Physical Implementation Lead - San Francisco - Stealth Startup

A fast-growing semiconductor technology company is developing an AI-driven chip-design platform. The team combines deep expertise across AI, semiconductor architecture, physical design and chip development, with a focus on building highly automated approaches to custom silicon development.

They're looking for an engineering leader to drive physical implementation for custom ASICs. This is an end-to-end technical leadership role setting up architecture, collaborating with the wider team and eventually building out your own too.

Core Responsibilities

• Deliver physical implementation for high-throughput, low-latency accelerators, optimised against key design KPIs.
• Define and drive layout strategy for IP, high-bandwidth interfaces, large on-chip SRAM and register structures.
• Lead deployment of AI-driven design-optimisation engines to automate macro placement, optimise clock and power distribution networks, and maximise PPA.
• Address physical-design challenges associated with AI workloads, including dynamic IR-drop, thermal-density mitigation and multi-GHz clock-tree synthesis.
• Apply reinforcement-learning principles across backend implementation stages to drive design optimisation.

Required Qualifications

• 5–10 years of physical-design experience, with a track record of taking complex, large-die SoCs or compute subsystems through tape‑out.
• Hands-on experience integrating AI-enabled design-optimisation tools into production implementation flows.
• Strong understanding of reinforcement-learning principles, including reward functions and optimisation techniques relevant to EDA and layout density.
• Proven expertise in physical sign-off, including STA, DRC, LVS and EM/IR on advanced process nodes.
• Expert‑level Python and Tcl skills for developing and automating custom infrastructure and layout‑iteration flows.

Ideal Candidate

• Strong technical ownership across the physical-design flow, from implementation strategy through sign-off.
• Experience working on large, performance‑critical AI, compute or accelerator designs.
• Comfortable operating at the intersection of physical design, automation and AI-driven optimisation.
• Hands‑on engineering mindset with the ability to solve complex backend challenges and drive execution.