Senior AI Compiler & Runtime Architect

HTEC Group; Palo Alto (CA); Hybrid; USD 200,000 - 350,000; Full time

Benefits offered by this job

Medical, dental and vision coverage

401(k) with Company match

Unlimited vacation

Paid holidays

Parental benefits

Employee assistance program

Job summary

HTEC Group, Inc. is seeking a senior engineer to build and optimize compiler and runtime infrastructure for AI workloads. You will enable efficient execution of ML models across GPUs, NPUs, TPUs, and custom accelerators in close collaboration with inference, systems, and hardware teams.

You will apply cutting-edge AI methods to improve software development, optimization, and hardware-aware design while tackling performance bottlenecks and advancing MLIR/LLVM-based toolchains.

Qualifications

• BSc, MSc, or PhD in Computer Science, Engineering, Mathematics.
• Strong programming in C/C++ and/or Python in Linux environments with common dev tools.
• Solid understanding of machine learning fundamentals and AI workloads.

Responsibilities

• Build and optimize compiler and runtime infrastructure for modern AI workloads.
• Enable efficient execution of ML models across GPUs, NPUs, TPUs, and accelerators.
• Apply AI technologies to improve software development, system optimization, and software-hardware co-design.
• Collaborate with inference, systems, and hardware teams to enhance co-design.
• Identify performance bottlenecks via profiling, benchmarking, and system analysis.

Skills

C/C++

Python

Machine learning fundamentals

Education

BSc, MSc, or PhD in Computer Science, Engineering, Mathematics

Tools

LLVM

MLIR

ONNX Runtime

Job description

HTEC Group, Inc. is seeking a senior engineer to build and optimize compiler and runtime infrastructure for AI workloads. You will enable efficient execution of ML models across GPUs, NPUs, TPUs, and custom accelerators in close collaboration with inference, systems, and hardware teams.

You will apply cutting-edge AI methods to improve software development, optimization, and hardware-aware design while tackling performance bottlenecks and advancing MLIR/LLVM-based toolchains.