Layout/Mask Designer

Apple; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

Apple in Austin, Texas seeks an Electrical Engineer to design complex digital circuit layouts in deep SubMicron CMOS. You will work with the Layout lead and circuit designers to review floorplans and optimize PPA, run verification tools, and ensure on-time delivery.

The role requires a Bachelor's in Electrical Engineering with 2 years of related experience and strong skills in RC delay, EM, and cross capacitance issues, using Cadence Virtuoso and CALIBRE tools.

Qualifications

• Bachelor’s degree in Electrical Engineering or related field with 2 years of related experience
• Experience with layout floor-planning and standard cell planning for best PPA
• Ability to interpret RC delay, electromigration, self-heating and cross capacitance issues
• Recognizing failure prone layout structures and collaborating with designers on shielding critical signals
• Creating layouts with a robust PG grid using IR simulations tools
• Using CALIBRE DRC, ERC, LVS, and DFM reports to finish layout(s)
• Using CADENCE Virtuoso layout design tools to draw layouts and increase productivity

Responsibilities

• Design complex custom layout for digital circuits in deep SubMicron CMOS technologies
• Review floorplans with Layout lead and circuit designers to optimize layouts
• Run layout verification tools and clean up megacells to meet specs
• Plan, schedule work and negotiate layout tradeoffs as needed
• Interpret LVS, DRC and ERC reports to find fastest path to complete layouts
• Collaborate with layout lead and circuit design team to ensure on-time deliverables
• Apply fixes from EMIR simulations to achieve robust power delivery
• Utilize automated P&R tools to speed up layout execution of digital designs

Skills

Layout floor-planning

Standard cell planning

Hierarchical layout assembly

RC delay

Electromigration

Self-heating

Cross capacitance

IR simulation tools

PG grid

CADENCE Virtuoso

Collaboration

On-time deliverables

Education

Bachelor’s degree in Electrical Engineering

Tools

CALIBRE DRC/ERC/LVS/DFM

Cadence Virtuoso

IR simulation tools

Job description

Summary

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Austin, Texas. Design complex custom layout for digital circuits in deep SubMicron CMOS technologies. Work with Layout lead and circuit designers to review and analyze floorplans of complex circuits. Responsible to run a complete set of layout design verification tools available and clean up megacells to match engineering specifications. Work with Layout lead and circuit design team to plan, schedule work and negotiate layout tradeoffs as needed. Interpret LVS, DRC and ERC report to find the fastest way to complete layouts. Utilize advanced CAD tools, mask design knowledge to layout corrections and robust physical design representation of circuits. Utilize advanced layout techniques to come up with best-in-class PPA for critical designs. Work with design lead to review EMIR simulations and apply necessary fixes to achieve robust power delivery. Utilize automated P&R tools to speed up the layout execution of digital designs. 40 hours/week.

Minimum Qualifications

Bachelor’s degree or foreign equivalent in Electrical Engineering or related field and 2 years of experience in the job offered or related occupation.2 years of experience with each of the following skills is required:Using layout floor-planning, standard cell planning and hierarchical layout assembly to generate best PPA (power, performance and area) layoutsResolving issues with RC delay, electromigration, self-heating and cross capacitance.Recognizing failure prone layout structures, working with designers for the best approach to problems like shielding critical signals, analyzing DFM yields and LOD effects.Creating layouts with a robust PG grid using IR simulations toolsCollaborating and communicating effectively with multi-functional teams to understand engineering spec and have on-time deliverablesInterpreting CALIBRE DRC, ERC, LVS, and DFM reports to finish layout(s)Using CADENCE virtuoso layout design tools to draw layouts and increased productivity

Preferred Qualifications

N/A