Digital Layout Design Engineer

Apple Inc.; Beaverton (OR); On-site; USD 120,000 - 180,000; Full time

Job summary

Apple Inc. in Beaverton, Oregon, seeks an experienced Digital Layout Designer to craft state-of-the-art ASIC layouts.

You will design complex custom digital macros, review floorplans, and work with the circuit and CAD teams to produce robust physical designs for next-generation chips. Ideal candidates bring a decade of layout experience, strong RC delay and electromigration knowledge, and proficiency with CALIBRE/ Mentor Graphics or Cadence tools.

Qualifications

• Bachelor's degree in a relevant field.
• 10+ years of relevant layout experience.
• Strong knowledge of RC delay, electromigration, self heating and cross capacitance.
• Familiarity with CALIBRE DRC/ERC/LVS and memory compiler layouts preferred.

Responsibilities

• Design complex custom digital layouts in deep SubMicron CMOS.
• Review floorplans and complex circuits with design teams.
• Run layout verification tools and ensure adherence to specifications.
• Interpret LVS/DRC/ERC results and implement layout improvements.
• Collaborate with circuit, integration, CAD, and technology teams.

Skills

Excellent communication

CMOS layout

CAD/EDA tools

Education

Bachelor's degree in relevant field

Tools

Mentor Graphics

Cadence

CALIBRE DRC/ERC/LVS

Job description

Do you have a passion for crafting entirely new solutions?As part of our Digital Design Engineering group, you’ll take imaginative and revolutionary ideas and determine how to turn them into reality! You and your team will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking ideas to the real world. Join us, and you’ll help design the tools that allow us to bring customers experiences they’ve never before envisioned.You will be part of an exciting silicon design group that is responsible for designing state-of-the art ASICs. We have an extraordinary opportunity for Digital Layout Designers!In this highly visible role, you will be a member of Apple’s custom layout team, working on the latest technology nodes to create extraordinary custom digital macros, libraries, etc. This is a fast paced work environment with endless learning opportunities working in the design team with members of integration, CAD, circuit and technology engineering.

Description

Imagine yourself at the center of our SOC design effort, collaborating with all fields, playing a strategic role of getting functional products to millions of customers quickly.You will have the opportunity to integrate and come-up with new ideas, as well as work with a team of hardworking engineers. As a member of the layout team of the microprocessor group, you will be responsible to deliver PDV clean layout, including the following:- Designing complex custom layout for digital circuits in deep SubMicron CMOS technologies.- Reviewing and analyzing floorplans and complex circuits with circuit designers.- Running a complete set of layout design verification tools available on megacells completed.- Working with the circuit design team to plan, schedule work and negotiate layout tradeoffs as needed.- Interpretation of LVS, DRC and ERC report to find the fastest way to complete layouts.- Exceed engineering specifications and expectations.- Use advanced CAD tools, mask design knowledge to layout corrections and robust physical design representation of circuits.

Minimum Qualifications

• Bachelors degree in relevant field of study plus 10 years of relevant experience

Preferred Qualifications

• We are looking for applicants experience in custom layout design of deep SubMicron CMOS circuits.
• High level proficiency in layout floorplanning, standard cell planning and hierarchical layout assembly.
• Good understanding of issues with RC delay, electromigration, self heating and cross capacitance.
• Recognize failure prone layout structures, dedicatedly work with designers for the best approach to problems.
• Excellent communication skills and able to work with multi-functional teams.
• Great skills on interpretation of CALIBRE DRC, ERC, LVS, etc. reports.
• Knowledge of MENTOR GRAPHICS or CADENCE layout tools
• Scripting skills in CSH, PERL or SKILL are considered a plus, but not required.
• Experience in layout automation is considered a plus, but not required.
• Experience in memory compiler development is considered a plus, but not required.
• Experience designing low noise, low power datapaths or Memory layout structures, etc.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

At Apple, we believe accessibility is a fundamental human right. You'll find that idea reflected in everything here - in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.

Learn about accessibility in Apple's workplace

Learn about reasonable accommodations for job applicants

Apple accepts applications to this posting on an ongoing basis.